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@@ -2583,6 +2583,20 @@ static void ack_apic_level(unsigned int irq)
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*/
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*/
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ack_APIC_irq();
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ack_APIC_irq();
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+ /* Tail end of version 0x11 I/O APIC bug workaround */
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+ if (!(v & (1 << (i & 0x1f)))) {
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+ atomic_inc(&irq_mis_count);
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+
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+ if (use_eoi_reg)
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+ eoi_ioapic_irq(desc);
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+ else {
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+ spin_lock(&ioapic_lock);
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+ __mask_and_edge_IO_APIC_irq(cfg);
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+ __unmask_and_level_IO_APIC_irq(cfg);
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+ spin_unlock(&ioapic_lock);
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+ }
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+ }
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+
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/* Now we can move and renable the irq */
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/* Now we can move and renable the irq */
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if (unlikely(do_unmask_irq)) {
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if (unlikely(do_unmask_irq)) {
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/* Only migrate the irq if the ack has been received.
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/* Only migrate the irq if the ack has been received.
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@@ -2616,20 +2630,6 @@ static void ack_apic_level(unsigned int irq)
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move_masked_irq(irq);
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move_masked_irq(irq);
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unmask_IO_APIC_irq_desc(desc);
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unmask_IO_APIC_irq_desc(desc);
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}
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}
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-
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- /* Tail end of version 0x11 I/O APIC bug workaround */
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- if (!(v & (1 << (i & 0x1f)))) {
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- atomic_inc(&irq_mis_count);
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-
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- if (use_eoi_reg)
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- eoi_ioapic_irq(desc);
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- else {
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- spin_lock(&ioapic_lock);
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- __mask_and_edge_IO_APIC_irq(cfg);
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- __unmask_and_level_IO_APIC_irq(cfg);
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- spin_unlock(&ioapic_lock);
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- }
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- }
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}
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}
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#ifdef CONFIG_INTR_REMAP
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#ifdef CONFIG_INTR_REMAP
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