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@@ -32,8 +32,13 @@
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#include "sdhci-pltfm.h"
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+/* Tegra SDHOST controller vendor register definitions */
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+#define SDHCI_TEGRA_VENDOR_MISC_CTRL 0x120
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+#define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20
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+
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#define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0)
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#define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1)
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+#define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2)
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struct sdhci_tegra_soc_data {
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struct sdhci_pltfm_data *pdata;
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@@ -120,6 +125,25 @@ static irqreturn_t carddetect_irq(int irq, void *data)
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return IRQ_HANDLED;
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};
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+static void tegra_sdhci_reset_exit(struct sdhci_host *host, u8 mask)
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+{
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+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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+ struct sdhci_tegra *tegra_host = pltfm_host->priv;
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+ const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
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+
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+ if (!(mask & SDHCI_RESET_ALL))
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+ return;
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+
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+ /* Erratum: Enable SDHCI spec v3.00 support */
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+ if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) {
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+ u32 misc_ctrl;
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+
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+ misc_ctrl = sdhci_readb(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);
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+ misc_ctrl |= SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300;
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+ sdhci_writeb(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL);
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+ }
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+}
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+
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static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@@ -148,6 +172,7 @@ static struct sdhci_ops tegra_sdhci_ops = {
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.read_w = tegra_sdhci_readw,
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.write_l = tegra_sdhci_writel,
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.platform_8bit_width = tegra_sdhci_8bit,
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+ .platform_reset_exit = tegra_sdhci_reset_exit,
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};
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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@@ -178,6 +203,7 @@ static struct sdhci_pltfm_data sdhci_tegra30_pdata = {
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static struct sdhci_tegra_soc_data soc_data_tegra30 = {
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.pdata = &sdhci_tegra30_pdata,
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+ .nvquirks = NVQUIRK_ENABLE_SDHCI_SPEC_300,
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};
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#endif
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