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@@ -82,17 +82,20 @@
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#define VSC_SATA_PORT_OFFSET 0x200
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/* Error interrupt status bit offsets */
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-#define VSC_SATA_INT_ERROR_E_OFFSET 2
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-#define VSC_SATA_INT_ERROR_P_OFFSET 4
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-#define VSC_SATA_INT_ERROR_T_OFFSET 5
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-#define VSC_SATA_INT_ERROR_M_OFFSET 1
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+#define VSC_SATA_INT_ERROR_CRC 0x40
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+#define VSC_SATA_INT_ERROR_T 0x20
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+#define VSC_SATA_INT_ERROR_P 0x10
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+#define VSC_SATA_INT_ERROR_R 0x8
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+#define VSC_SATA_INT_ERROR_E 0x4
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+#define VSC_SATA_INT_ERROR_M 0x2
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+#define VSC_SATA_INT_PHY_CHANGE 0x1
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+#define VSC_SATA_INT_ERROR (VSC_SATA_INT_ERROR_CRC | VSC_SATA_INT_ERROR_T | \
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+ VSC_SATA_INT_ERROR_P | VSC_SATA_INT_ERROR_R | \
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+ VSC_SATA_INT_ERROR_E | VSC_SATA_INT_ERROR_M | \
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+ VSC_SATA_INT_PHY_CHANGE)
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+
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#define is_vsc_sata_int_err(port_idx, int_status) \
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- (int_status & ((1 << (VSC_SATA_INT_ERROR_E_OFFSET + (8 * port_idx))) | \
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- (1 << (VSC_SATA_INT_ERROR_P_OFFSET + (8 * port_idx))) | \
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- (1 << (VSC_SATA_INT_ERROR_T_OFFSET + (8 * port_idx))) | \
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- (1 << (VSC_SATA_INT_ERROR_M_OFFSET + (8 * port_idx))) \
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- )\
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- )
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+ (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
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static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
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@@ -215,14 +218,6 @@ static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
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ap = host_set->ports[i];
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- if (is_vsc_sata_int_err(i, int_status)) {
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- u32 err_status;
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- printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
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- err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
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- vsc_sata_scr_write(ap, SCR_ERROR, err_status);
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- handled++;
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- }
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-
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if (ap && !(ap->flags &
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(ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
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struct ata_queued_cmd *qc;
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@@ -230,12 +225,26 @@ static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
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qc = ata_qc_from_tag(ap, ap->active_tag);
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if (qc && (!(qc->tf.ctl & ATA_NIEN))) {
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handled += ata_host_intr(ap, qc);
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- } else {
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- printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
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+ } else if (is_vsc_sata_int_err(i, int_status)) {
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+ /*
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+ * On some chips (i.e. Intel 31244), an error
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+ * interrupt will sneak in at initialization
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+ * time (phy state changes). Clearing the SCR
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+ * error register is not required, but it prevents
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+ * the phy state change interrupts from recurring
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+ * later.
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+ */
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+ u32 err_status;
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+ err_status = vsc_sata_scr_read(ap, SCR_ERROR);
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+ printk(KERN_DEBUG "%s: clearing interrupt, "
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+ "status %x; sata err status %x\n",
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+ __FUNCTION__,
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+ int_status, err_status);
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+ vsc_sata_scr_write(ap, SCR_ERROR, err_status);
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+ /* Clear interrupt status */
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ata_chk_status(ap);
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handled++;
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}
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-
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}
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}
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}
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