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@@ -403,14 +403,15 @@ void iwl_trans_set_wr_ptrs(struct iwl_trans *trans,
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iwl_write_prph(bus(trans), SCD_QUEUE_RDPTR(txq_id), index);
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}
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-void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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+void iwl_trans_tx_queue_set_status(struct iwl_trans *trans,
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struct iwl_tx_queue *txq,
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int tx_fifo_id, int scd_retry)
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{
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int txq_id = txq->q.id;
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- int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
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+ int active =
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+ test_bit(txq_id, &priv(trans)->txq_ctx_active_msk) ? 1 : 0;
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- iwl_write_prph(bus(priv), SCD_QUEUE_STATUS_BITS(txq_id),
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+ iwl_write_prph(bus(trans), SCD_QUEUE_STATUS_BITS(txq_id),
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(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
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(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
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(1 << SCD_QUEUE_STTS_REG_POS_WSL) |
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@@ -418,7 +419,7 @@ void iwl_trans_tx_queue_set_status(struct iwl_priv *priv,
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txq->sched_retry = scd_retry;
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- IWL_DEBUG_INFO(priv, "%s %s Queue %d on FIFO %d\n",
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+ IWL_DEBUG_INFO(trans, "%s %s Queue %d on FIFO %d\n",
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active ? "Activate" : "Deactivate",
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scd_retry ? "BA" : "AC/CMD", txq_id, tx_fifo_id);
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}
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@@ -434,16 +435,15 @@ static inline int get_fifo_from_tid(struct iwl_trans_pcie *trans_pcie,
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return -EINVAL;
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}
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-void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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- enum iwl_rxon_context_id ctx, int sta_id,
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- int tid, int frame_limit)
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+void iwl_trans_pcie_tx_agg_setup(struct iwl_trans *trans,
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+ enum iwl_rxon_context_id ctx, int sta_id,
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+ int tid, int frame_limit)
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{
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int tx_fifo, txq_id, ssn_idx;
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u16 ra_tid;
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unsigned long flags;
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struct iwl_tid_data *tid_data;
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- struct iwl_trans *trans = trans(priv);
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struct iwl_trans_pcie *trans_pcie =
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IWL_TRANS_GET_PCIE_TRANS(trans);
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@@ -458,15 +458,15 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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return;
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}
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- spin_lock_irqsave(&priv->shrd->sta_lock, flags);
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- tid_data = &priv->shrd->tid_data[sta_id][tid];
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+ spin_lock_irqsave(&trans->shrd->sta_lock, flags);
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+ tid_data = &trans->shrd->tid_data[sta_id][tid];
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ssn_idx = SEQ_TO_SN(tid_data->seq_number);
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txq_id = tid_data->agg.txq_id;
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- spin_unlock_irqrestore(&priv->shrd->sta_lock, flags);
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+ spin_unlock_irqrestore(&trans->shrd->sta_lock, flags);
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ra_tid = BUILD_RAxTID(sta_id, tid);
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- spin_lock_irqsave(&priv->shrd->lock, flags);
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+ spin_lock_irqsave(&trans->shrd->lock, flags);
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/* Stop this Tx queue before configuring it */
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iwlagn_tx_queue_stop_scheduler(trans, txq_id);
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@@ -475,19 +475,19 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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iwlagn_tx_queue_set_q2ratid(trans, ra_tid, txq_id);
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/* Set this queue as a chain-building queue */
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- iwl_set_bits_prph(bus(priv), SCD_QUEUECHAIN_SEL, (1<<txq_id));
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+ iwl_set_bits_prph(bus(trans), SCD_QUEUECHAIN_SEL, (1<<txq_id));
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/* enable aggregations for the queue */
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- iwl_set_bits_prph(bus(priv), SCD_AGGR_SEL, (1<<txq_id));
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+ iwl_set_bits_prph(bus(trans), SCD_AGGR_SEL, (1<<txq_id));
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/* Place first TFD at index corresponding to start sequence number.
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* Assumes that ssn_idx is valid (!= 0xFFF) */
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- priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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- priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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+ priv(trans)->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
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+ priv(trans)->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
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iwl_trans_set_wr_ptrs(trans, txq_id, ssn_idx);
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/* Set up Tx window size and frame limit for this queue */
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- iwl_write_targ_mem(bus(priv), trans_pcie->scd_base_addr +
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+ iwl_write_targ_mem(bus(trans), trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
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sizeof(u32),
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((frame_limit <<
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@@ -497,15 +497,16 @@ void iwl_trans_pcie_txq_agg_setup(struct iwl_priv *priv,
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
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SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
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- iwl_set_bits_prph(bus(priv), SCD_INTERRUPT_MASK, (1 << txq_id));
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+ iwl_set_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
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/* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
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- iwl_trans_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
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+ iwl_trans_tx_queue_set_status(trans, &priv(trans)->txq[txq_id],
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+ tx_fifo, 1);
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- priv->txq[txq_id].sta_id = sta_id;
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- priv->txq[txq_id].tid = tid;
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+ priv(trans)->txq[txq_id].sta_id = sta_id;
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+ priv(trans)->txq[txq_id].tid = tid;
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- spin_unlock_irqrestore(&priv->shrd->lock, flags);
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+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
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}
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/*
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@@ -574,8 +575,7 @@ void iwl_trans_pcie_txq_agg_disable(struct iwl_trans *trans, int txq_id)
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iwl_clear_bits_prph(bus(trans), SCD_INTERRUPT_MASK, (1 << txq_id));
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iwl_txq_ctx_deactivate(priv(trans), txq_id);
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- iwl_trans_tx_queue_set_status(priv(trans),
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- &priv(trans)->txq[txq_id], 0, 0);
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+ iwl_trans_tx_queue_set_status(trans, &priv(trans)->txq[txq_id], 0, 0);
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}
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int iwl_trans_pcie_tx_agg_disable(struct iwl_trans *trans,
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