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@@ -119,7 +119,7 @@ struct pxa3xx_nand_info {
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struct nand_chip nand_chip;
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struct platform_device *pdev;
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- struct pxa3xx_nand_flash *flash_info;
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+ const struct pxa3xx_nand_flash *flash_info;
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struct clk *clk;
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void __iomem *mmio_base;
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@@ -158,6 +158,13 @@ struct pxa3xx_nand_info {
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uint32_t ndcb0;
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uint32_t ndcb1;
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uint32_t ndcb2;
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+
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+ /* calculated from pxa3xx_nand_flash data */
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+ size_t oob_size;
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+ size_t read_id_bytes;
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+
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+ unsigned int col_addr_cycles;
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+ unsigned int row_addr_cycles;
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};
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static int use_dma = 1;
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@@ -335,7 +342,7 @@ static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
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static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
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uint16_t cmd, int column, int page_addr)
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{
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- struct pxa3xx_nand_flash *f = info->flash_info;
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+ const struct pxa3xx_nand_flash *f = info->flash_info;
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const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
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/* calculate data size */
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@@ -354,14 +361,14 @@ static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
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info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
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info->ndcb1 = 0;
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info->ndcb2 = 0;
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- info->ndcb0 |= NDCB0_ADDR_CYC(f->row_addr_cycles + f->col_addr_cycles);
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+ info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
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- if (f->col_addr_cycles == 2) {
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+ if (info->col_addr_cycles == 2) {
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/* large block, 2 cycles for column address
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* row address starts from 3rd cycle
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*/
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info->ndcb1 |= (page_addr << 16) | (column & 0xffff);
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- if (f->row_addr_cycles == 3)
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+ if (info->row_addr_cycles == 3)
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info->ndcb2 = (page_addr >> 16) & 0xff;
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} else
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/* small block, 1 cycles for column address
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@@ -622,7 +629,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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struct pxa3xx_nand_info *info = mtd->priv;
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- struct pxa3xx_nand_flash *flash_info = info->flash_info;
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+ const struct pxa3xx_nand_flash *flash_info = info->flash_info;
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const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
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int ret;
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@@ -701,7 +708,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
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info->use_dma = 0; /* force PIO read */
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info->buf_start = 0;
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info->buf_count = (command == NAND_CMD_READID) ?
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- flash_info->read_id_bytes : 1;
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+ info->read_id_bytes : 1;
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if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
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cmdset->read_id : cmdset->read_status))
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@@ -842,7 +849,7 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
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static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
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{
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- struct pxa3xx_nand_flash *f = info->flash_info;
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+ const struct pxa3xx_nand_flash *f = info->flash_info;
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const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
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uint32_t ndcr;
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uint8_t id_buff[8];
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@@ -872,7 +879,7 @@ fail_timeout:
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}
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static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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- struct pxa3xx_nand_flash *f)
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+ const struct pxa3xx_nand_flash *f)
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{
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struct platform_device *pdev = info->pdev;
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struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
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@@ -885,25 +892,25 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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return -EINVAL;
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/* calculate flash information */
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- f->oob_size = (f->page_size == 2048) ? 64 : 16;
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- f->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
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+ info->oob_size = (f->page_size == 2048) ? 64 : 16;
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+ info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
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/* calculate addressing information */
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- f->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
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+ info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
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if (f->num_blocks * f->page_per_block > 65536)
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- f->row_addr_cycles = 3;
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+ info->row_addr_cycles = 3;
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else
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- f->row_addr_cycles = 2;
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+ info->row_addr_cycles = 2;
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ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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- ndcr |= (f->col_addr_cycles == 2) ? NDCR_RA_START : 0;
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+ ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
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ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
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ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
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ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
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ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
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- ndcr |= NDCR_RD_ID_CNT(f->read_id_bytes);
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+ ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
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ndcr |= NDCR_SPARE_EN; /* enable spare by default */
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info->reg_ndcr = ndcr;
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@@ -916,7 +923,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
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const struct pxa3xx_nand_platform_data *pdata)
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{
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- struct pxa3xx_nand_flash *f;
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+ const struct pxa3xx_nand_flash *f;
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uint32_t id;
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int i;
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@@ -1011,7 +1018,7 @@ static struct nand_ecclayout hw_largepage_ecclayout = {
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static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
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struct pxa3xx_nand_info *info)
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{
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- struct pxa3xx_nand_flash *f = info->flash_info;
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+ const struct pxa3xx_nand_flash *f = info->flash_info;
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struct nand_chip *this = &info->nand_chip;
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this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
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