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@@ -10,6 +10,8 @@
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/percpu.h>
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+#include <linux/irq.h>
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+#include <linux/msi.h>
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#include <asm/pbm.h>
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#include <asm/iommu.h>
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@@ -1074,6 +1076,443 @@ static void pci_sun4v_get_bus_range(struct pci_pbm_info *pbm)
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}
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+#ifdef CONFIG_PCI_MSI
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+struct pci_sun4v_msiq_entry {
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+ u64 version_type;
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+#define MSIQ_VERSION_MASK 0xffffffff00000000UL
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+#define MSIQ_VERSION_SHIFT 32
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+#define MSIQ_TYPE_MASK 0x00000000000000ffUL
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+#define MSIQ_TYPE_SHIFT 0
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+#define MSIQ_TYPE_NONE 0x00
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+#define MSIQ_TYPE_MSG 0x01
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+#define MSIQ_TYPE_MSI32 0x02
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+#define MSIQ_TYPE_MSI64 0x03
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+#define MSIQ_TYPE_INTX 0x08
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+#define MSIQ_TYPE_NONE2 0xff
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+
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+ u64 intx_sysino;
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+ u64 reserved1;
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+ u64 stick;
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+ u64 req_id; /* bus/device/func */
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+#define MSIQ_REQID_BUS_MASK 0xff00UL
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+#define MSIQ_REQID_BUS_SHIFT 8
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+#define MSIQ_REQID_DEVICE_MASK 0x00f8UL
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+#define MSIQ_REQID_DEVICE_SHIFT 3
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+#define MSIQ_REQID_FUNC_MASK 0x0007UL
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+#define MSIQ_REQID_FUNC_SHIFT 0
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+
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+ u64 msi_address;
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+
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+ /* The format of this value is message type dependant.
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+ * For MSI bits 15:0 are the data from the MSI packet.
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+ * For MSI-X bits 31:0 are the data from the MSI packet.
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+ * For MSG, the message code and message routing code where:
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+ * bits 39:32 is the bus/device/fn of the msg target-id
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+ * bits 18:16 is the message routing code
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+ * bits 7:0 is the message code
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+ * For INTx the low order 2-bits are:
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+ * 00 - INTA
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+ * 01 - INTB
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+ * 10 - INTC
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+ * 11 - INTD
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+ */
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+ u64 msi_data;
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+
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+ u64 reserved2;
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+};
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+
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+/* For now this just runs as a pre-handler for the real interrupt handler.
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+ * So we just walk through the queue and ACK all the entries, update the
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+ * head pointer, and return.
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+ *
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+ * In the longer term it would be nice to do something more integrated
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+ * wherein we can pass in some of this MSI info to the drivers. This
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+ * would be most useful for PCIe fabric error messages, although we could
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+ * invoke those directly from the loop here in order to pass the info around.
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+ */
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+static void pci_sun4v_msi_prehandler(unsigned int ino, void *data1, void *data2)
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+{
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+ struct pci_pbm_info *pbm = data1;
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+ struct pci_sun4v_msiq_entry *base, *ep;
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+ unsigned long msiqid, orig_head, head, type, err;
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+
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+ msiqid = (unsigned long) data2;
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+
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+ head = 0xdeadbeef;
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+ err = pci_sun4v_msiq_gethead(pbm->devhandle, msiqid, &head);
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+ if (unlikely(err))
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+ goto hv_error_get;
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+
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+ if (unlikely(head >= (pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry))))
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+ goto bad_offset;
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+
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+ head /= sizeof(struct pci_sun4v_msiq_entry);
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+ orig_head = head;
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+ base = (pbm->msi_queues + ((msiqid - pbm->msiq_first) *
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+ (pbm->msiq_ent_count *
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+ sizeof(struct pci_sun4v_msiq_entry))));
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+ ep = &base[head];
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+ while ((ep->version_type & MSIQ_TYPE_MASK) != 0) {
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+ type = (ep->version_type & MSIQ_TYPE_MASK) >> MSIQ_TYPE_SHIFT;
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+ if (unlikely(type != MSIQ_TYPE_MSI32 &&
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+ type != MSIQ_TYPE_MSI64))
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+ goto bad_type;
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+
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+ pci_sun4v_msi_setstate(pbm->devhandle,
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+ ep->msi_data /* msi_num */,
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+ HV_MSISTATE_IDLE);
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+
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+ /* Clear the entry. */
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+ ep->version_type &= ~MSIQ_TYPE_MASK;
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+
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+ /* Go to next entry in ring. */
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+ head++;
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+ if (head >= pbm->msiq_ent_count)
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+ head = 0;
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+ ep = &base[head];
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+ }
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+
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+ if (likely(head != orig_head)) {
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+ /* ACK entries by updating head pointer. */
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+ head *= sizeof(struct pci_sun4v_msiq_entry);
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+ err = pci_sun4v_msiq_sethead(pbm->devhandle, msiqid, head);
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+ if (unlikely(err))
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+ goto hv_error_set;
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+ }
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+ return;
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+
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+hv_error_set:
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+ printk(KERN_EMERG "MSI: Hypervisor set head gives error %lu\n", err);
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+ goto hv_error_cont;
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+
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+hv_error_get:
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+ printk(KERN_EMERG "MSI: Hypervisor get head gives error %lu\n", err);
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+
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+hv_error_cont:
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+ printk(KERN_EMERG "MSI: devhandle[%x] msiqid[%lx] head[%lu]\n",
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+ pbm->devhandle, msiqid, head);
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+ return;
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+
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+bad_offset:
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+ printk(KERN_EMERG "MSI: Hypervisor gives bad offset %lx max(%lx)\n",
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+ head, pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry));
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+ return;
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+
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+bad_type:
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+ printk(KERN_EMERG "MSI: Entry has bad type %lx\n", type);
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+ return;
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+}
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+
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+static int msi_bitmap_alloc(struct pci_pbm_info *pbm)
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+{
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+ unsigned long size, bits_per_ulong;
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+
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+ bits_per_ulong = sizeof(unsigned long) * 8;
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+ size = (pbm->msi_num + (bits_per_ulong - 1)) & ~(bits_per_ulong - 1);
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+ size /= 8;
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+ BUG_ON(size % sizeof(unsigned long));
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+
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+ pbm->msi_bitmap = kzalloc(size, GFP_KERNEL);
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+ if (!pbm->msi_bitmap)
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+ return -ENOMEM;
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+
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+ return 0;
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+}
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+
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+static void msi_bitmap_free(struct pci_pbm_info *pbm)
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+{
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+ kfree(pbm->msi_bitmap);
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+ pbm->msi_bitmap = NULL;
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+}
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+
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+static int msi_queue_alloc(struct pci_pbm_info *pbm)
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+{
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+ unsigned long q_size, alloc_size, pages, order;
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+ int i;
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+
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+ q_size = pbm->msiq_ent_count * sizeof(struct pci_sun4v_msiq_entry);
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+ alloc_size = (pbm->msiq_num * q_size);
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+ order = get_order(alloc_size);
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+ pages = __get_free_pages(GFP_KERNEL | __GFP_COMP, order);
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+ if (pages == 0UL) {
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+ printk(KERN_ERR "MSI: Cannot allocate MSI queues (o=%lu).\n",
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+ order);
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+ return -ENOMEM;
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+ }
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+ memset((char *)pages, 0, PAGE_SIZE << order);
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+ pbm->msi_queues = (void *) pages;
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+
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+ for (i = 0; i < pbm->msiq_num; i++) {
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+ unsigned long err, base = __pa(pages + (i * q_size));
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+ unsigned long ret1, ret2;
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+
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+ err = pci_sun4v_msiq_conf(pbm->devhandle,
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+ pbm->msiq_first + i,
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+ base, pbm->msiq_ent_count);
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+ if (err) {
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+ printk(KERN_ERR "MSI: msiq register fails (err=%lu)\n",
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+ err);
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+ goto h_error;
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+ }
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+
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+ err = pci_sun4v_msiq_info(pbm->devhandle,
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+ pbm->msiq_first + i,
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+ &ret1, &ret2);
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+ if (err) {
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+ printk(KERN_ERR "MSI: Cannot read msiq (err=%lu)\n",
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+ err);
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+ goto h_error;
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+ }
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+ if (ret1 != base || ret2 != pbm->msiq_ent_count) {
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+ printk(KERN_ERR "MSI: Bogus qconf "
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+ "expected[%lx:%x] got[%lx:%lx]\n",
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+ base, pbm->msiq_ent_count,
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+ ret1, ret2);
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+ goto h_error;
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+ }
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+ }
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+
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+ return 0;
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+
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+h_error:
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+ free_pages(pages, order);
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+ return -EINVAL;
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+}
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+
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+static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
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+{
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+ u32 *val;
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+ int len;
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+
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+ val = of_get_property(pbm->prom_node, "#msi-eqs", &len);
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+ if (!val || len != 4)
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+ goto no_msi;
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+ pbm->msiq_num = *val;
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+ if (pbm->msiq_num) {
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+ struct msiq_prop {
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+ u32 first_msiq;
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+ u32 num_msiq;
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+ u32 first_devino;
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+ } *mqp;
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+ struct msi_range_prop {
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+ u32 first_msi;
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+ u32 num_msi;
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+ } *mrng;
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+ struct addr_range_prop {
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+ u32 msi32_high;
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+ u32 msi32_low;
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+ u32 msi32_len;
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+ u32 msi64_high;
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+ u32 msi64_low;
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+ u32 msi64_len;
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+ } *arng;
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+
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+ val = of_get_property(pbm->prom_node, "msi-eq-size", &len);
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+ if (!val || len != 4)
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+ goto no_msi;
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+
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+ pbm->msiq_ent_count = *val;
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+
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+ mqp = of_get_property(pbm->prom_node,
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+ "msi-eq-to-devino", &len);
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+ if (!mqp || len != sizeof(struct msiq_prop))
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+ goto no_msi;
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+
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+ pbm->msiq_first = mqp->first_msiq;
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+ pbm->msiq_first_devino = mqp->first_devino;
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+
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+ val = of_get_property(pbm->prom_node, "#msi", &len);
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+ if (!val || len != 4)
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+ goto no_msi;
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+ pbm->msi_num = *val;
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+
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+ mrng = of_get_property(pbm->prom_node, "msi-ranges", &len);
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+ if (!mrng || len != sizeof(struct msi_range_prop))
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+ goto no_msi;
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+ pbm->msi_first = mrng->first_msi;
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+
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+ val = of_get_property(pbm->prom_node, "msi-data-mask", &len);
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+ if (!val || len != 4)
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+ goto no_msi;
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+ pbm->msi_data_mask = *val;
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+
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+ val = of_get_property(pbm->prom_node, "msix-data-width", &len);
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+ if (!val || len != 4)
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+ goto no_msi;
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+ pbm->msix_data_width = *val;
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+
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+ arng = of_get_property(pbm->prom_node, "msi-address-ranges",
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+ &len);
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+ if (!arng || len != sizeof(struct addr_range_prop))
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+ goto no_msi;
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+ pbm->msi32_start = ((u64)arng->msi32_high << 32) |
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+ (u64) arng->msi32_low;
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+ pbm->msi64_start = ((u64)arng->msi64_high << 32) |
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+ (u64) arng->msi64_low;
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+ pbm->msi32_len = arng->msi32_len;
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+ pbm->msi64_len = arng->msi64_len;
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+
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+ if (msi_bitmap_alloc(pbm))
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+ goto no_msi;
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+
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+ if (msi_queue_alloc(pbm)) {
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+ msi_bitmap_free(pbm);
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+ goto no_msi;
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+ }
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+
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+ printk(KERN_INFO "%s: MSI Queue first[%u] num[%u] count[%u] "
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+ "devino[0x%x]\n",
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+ pbm->name,
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+ pbm->msiq_first, pbm->msiq_num,
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+ pbm->msiq_ent_count,
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+ pbm->msiq_first_devino);
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+ printk(KERN_INFO "%s: MSI first[%u] num[%u] mask[0x%x] "
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+ "width[%u]\n",
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+ pbm->name,
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+ pbm->msi_first, pbm->msi_num, pbm->msi_data_mask,
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+ pbm->msix_data_width);
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+ printk(KERN_INFO "%s: MSI addr32[0x%lx:0x%x] "
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+ "addr64[0x%lx:0x%x]\n",
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+ pbm->name,
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+ pbm->msi32_start, pbm->msi32_len,
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+ pbm->msi64_start, pbm->msi64_len);
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+ printk(KERN_INFO "%s: MSI queues at RA [%p]\n",
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+ pbm->name,
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+ pbm->msi_queues);
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+ }
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+
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+ return;
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+
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+no_msi:
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+ pbm->msiq_num = 0;
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+ printk(KERN_INFO "%s: No MSI support.\n", pbm->name);
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+}
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+
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+static int alloc_msi(struct pci_pbm_info *pbm)
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+{
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+ int i;
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+
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+ for (i = 0; i < pbm->msi_num; i++) {
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+ if (!test_and_set_bit(i, pbm->msi_bitmap))
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+ return i + pbm->msi_first;
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+ }
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+
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+ return -ENOENT;
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+}
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+
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+static void free_msi(struct pci_pbm_info *pbm, int msi_num)
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+{
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+ msi_num -= pbm->msi_first;
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+ clear_bit(msi_num, pbm->msi_bitmap);
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+}
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+
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+static int pci_sun4v_setup_msi_irq(unsigned int *virt_irq_p,
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+ struct pci_dev *pdev,
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+ struct msi_desc *entry)
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+{
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+ struct pcidev_cookie *pcp = pdev->sysdata;
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+ struct pci_pbm_info *pbm = pcp->pbm;
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+ unsigned long devino, msiqid;
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+ struct msi_msg msg;
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+ int msi_num, err;
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+
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+ *virt_irq_p = 0;
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+
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+ msi_num = alloc_msi(pbm);
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+ if (msi_num < 0)
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+ return msi_num;
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+
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+ devino = sun4v_build_msi(pbm->devhandle, virt_irq_p,
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+ pbm->msiq_first_devino,
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+ (pbm->msiq_first_devino +
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+ pbm->msiq_num));
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+ err = -ENOMEM;
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+ if (!devino)
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+ goto out_err;
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+
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+ set_irq_msi(*virt_irq_p, entry);
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+
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+ msiqid = ((devino - pbm->msiq_first_devino) +
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+ pbm->msiq_first);
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+
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+ err = -EINVAL;
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+ if (pci_sun4v_msiq_setstate(pbm->devhandle, msiqid, HV_MSIQSTATE_IDLE))
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+ if (err)
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+ goto out_err;
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+
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+ if (pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_VALID))
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+ goto out_err;
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+
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+ if (pci_sun4v_msi_setmsiq(pbm->devhandle,
|
|
|
+ msi_num, msiqid,
|
|
|
+ (entry->msi_attrib.is_64 ?
|
|
|
+ HV_MSITYPE_MSI64 : HV_MSITYPE_MSI32)))
|
|
|
+ goto out_err;
|
|
|
+
|
|
|
+ if (pci_sun4v_msi_setstate(pbm->devhandle, msi_num, HV_MSISTATE_IDLE))
|
|
|
+ goto out_err;
|
|
|
+
|
|
|
+ if (pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_VALID))
|
|
|
+ goto out_err;
|
|
|
+
|
|
|
+ pcp->msi_num = msi_num;
|
|
|
+
|
|
|
+ if (entry->msi_attrib.is_64) {
|
|
|
+ msg.address_hi = pbm->msi64_start >> 32;
|
|
|
+ msg.address_lo = pbm->msi64_start & 0xffffffff;
|
|
|
+ } else {
|
|
|
+ msg.address_hi = 0;
|
|
|
+ msg.address_lo = pbm->msi32_start;
|
|
|
+ }
|
|
|
+ msg.data = msi_num;
|
|
|
+ write_msi_msg(*virt_irq_p, &msg);
|
|
|
+
|
|
|
+ irq_install_pre_handler(*virt_irq_p,
|
|
|
+ pci_sun4v_msi_prehandler,
|
|
|
+ pbm, (void *) msiqid);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+out_err:
|
|
|
+ free_msi(pbm, msi_num);
|
|
|
+ sun4v_destroy_msi(*virt_irq_p);
|
|
|
+ *virt_irq_p = 0;
|
|
|
+ return err;
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+static void pci_sun4v_teardown_msi_irq(unsigned int virt_irq,
|
|
|
+ struct pci_dev *pdev)
|
|
|
+{
|
|
|
+ struct pcidev_cookie *pcp = pdev->sysdata;
|
|
|
+ struct pci_pbm_info *pbm = pcp->pbm;
|
|
|
+ unsigned long msiqid, err;
|
|
|
+ unsigned int msi_num;
|
|
|
+
|
|
|
+ msi_num = pcp->msi_num;
|
|
|
+ err = pci_sun4v_msi_getmsiq(pbm->devhandle, msi_num, &msiqid);
|
|
|
+ if (err) {
|
|
|
+ printk(KERN_ERR "%s: getmsiq gives error %lu\n",
|
|
|
+ pbm->name, err);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ pci_sun4v_msi_setvalid(pbm->devhandle, msi_num, HV_MSIVALID_INVALID);
|
|
|
+ pci_sun4v_msiq_setvalid(pbm->devhandle, msiqid, HV_MSIQ_INVALID);
|
|
|
+
|
|
|
+ free_msi(pbm, msi_num);
|
|
|
+
|
|
|
+ /* The sun4v_destroy_msi() will liberate the devino and thus the MSIQ
|
|
|
+ * allocation.
|
|
|
+ */
|
|
|
+ sun4v_destroy_msi(virt_irq);
|
|
|
+}
|
|
|
+#else /* CONFIG_PCI_MSI */
|
|
|
+static void pci_sun4v_msi_init(struct pci_pbm_info *pbm)
|
|
|
+{
|
|
|
+}
|
|
|
+#endif /* !(CONFIG_PCI_MSI) */
|
|
|
+
|
|
|
static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 devhandle)
|
|
|
{
|
|
|
struct pci_pbm_info *pbm;
|
|
@@ -1119,6 +1558,7 @@ static void pci_sun4v_pbm_init(struct pci_controller_info *p, struct device_node
|
|
|
|
|
|
pci_sun4v_get_bus_range(pbm);
|
|
|
pci_sun4v_iommu_init(pbm);
|
|
|
+ pci_sun4v_msi_init(pbm);
|
|
|
|
|
|
pdev_htab_populate(pbm);
|
|
|
}
|
|
@@ -1187,6 +1627,10 @@ void sun4v_pci_init(struct device_node *dp, char *model_name)
|
|
|
p->scan_bus = pci_sun4v_scan_bus;
|
|
|
p->base_address_update = pci_sun4v_base_address_update;
|
|
|
p->resource_adjust = pci_sun4v_resource_adjust;
|
|
|
+#ifdef CONFIG_PCI_MSI
|
|
|
+ p->setup_msi_irq = pci_sun4v_setup_msi_irq;
|
|
|
+ p->teardown_msi_irq = pci_sun4v_teardown_msi_irq;
|
|
|
+#endif
|
|
|
p->pci_ops = &pci_sun4v_ops;
|
|
|
|
|
|
/* Like PSYCHO and SCHIZO we have a 2GB aligned area
|