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@@ -18,6 +18,7 @@
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#include <asm/pm.h>
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#include <mach/pm.h>
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#include <asm/blackfin.h>
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+#include <asm/mem_init.h>
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/***********************************************************/
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/* */
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@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void)
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}
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__attribute__((l1_text))
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-void bfin_deepsleep(unsigned long mask)
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+void bf609_ddr_sr(void)
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{
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- uint32_t dpm0_ctl;
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-
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- bfin_write32(DPM0_WAKE_EN, 0x10);
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- bfin_write32(DPM0_WAKE_POL, 0x10);
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- dpm0_ctl = 0x00000008;
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- bfin_write32(DPM0_CTL, dpm0_ctl);
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- SSYNC();
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- __asm__ __volatile__( \
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- ".align 8;" \
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- "idle;" \
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- : : \
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- );
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-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
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- __asm__ __volatile__(
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- "R0 = 0;"
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- "CYCLES = R0;"
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- "CYCLES2 = R0;"
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- "R0 = SYSCFG;"
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- "BITSET(R0, 1);"
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- "SYSCFG = R0;"
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- : : : "R0"
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- );
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-#endif
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-
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+ dmc_enter_self_refresh();
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}
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__attribute__((l1_text))
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-void bf609_ddr_sr(void)
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+void bf609_ddr_sr_exit(void)
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{
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- uint32_t reg;
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-
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- reg = bfin_read_DMC0_CTL();
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- reg |= 0x8;
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- bfin_write_DMC0_CTL(reg);
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+ dmc_exit_self_refresh();
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- while (!(bfin_read_DMC0_STAT() & 0x8))
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+ /* After wake up from deep sleep and exit DDR from self refress mode,
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+ * should wait till CGU PLL is locked.
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+ */
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+ while (bfin_read32(CGU0_STAT) & CLKSALGN)
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continue;
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}
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__attribute__((l1_text))
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-void bf609_ddr_sr_exit(void)
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+void bf609_resume_ccbuf(void)
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{
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- uint32_t reg;
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- while (!(bfin_read_DMC0_STAT() & 0x1))
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- continue;
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+ bfin_write32(DPM0_CCBF_EN, 3);
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+ bfin_write32(DPM0_CTL, 2);
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- reg = bfin_read_DMC0_CTL();
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- reg &= ~0x8;
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- bfin_write_DMC0_CTL(reg);
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-
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- while ((bfin_read_DMC0_STAT() & 0x8))
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- continue;
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+ while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
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}
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__attribute__((l1_text))
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@@ -208,6 +179,17 @@ void bfin_hibernate_syscontrol(void)
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#else
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# define SIC_SYSIRQ(irq) ((irq) - IVG15)
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#endif
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+asmlinkage void enter_deepsleep(void);
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+
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+__attribute__((l1_text))
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+void bfin_deepsleep(unsigned long mask)
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+{
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+ bfin_write32(DPM0_WAKE_EN, 0x10);
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+ bfin_write32(DPM0_WAKE_POL, 0x10);
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+ SSYNC();
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+ enter_deepsleep();
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+}
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+
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void bfin_hibernate(unsigned long mask)
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{
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bfin_write32(DPM0_WAKE_EN, 0x10);
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@@ -215,8 +197,6 @@ void bfin_hibernate(unsigned long mask)
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bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
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bfin_write32(DPM0_HIB_DIS, 0xFFFF);
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- printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
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-
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bf609_hibernate();
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}
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@@ -294,6 +274,7 @@ void bf609_cpu_pm_enter(suspend_state_t state)
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else {
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bfin_hibernate(wakeup);
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}
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+
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}
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int bf609_cpu_pm_prepare(void)
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@@ -320,21 +301,18 @@ static irqreturn_t test_isr(int irq, void *dev_id)
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static irqreturn_t dpm0_isr(int irq, void *dev_id)
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{
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- uint32_t wake_stat;
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-
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- wake_stat = bfin_read32(DPM0_WAKE_STAT);
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- printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
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-
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- bfin_write32(DPM0_WAKE_STAT, wake_stat);
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+ bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
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+ bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
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return IRQ_HANDLED;
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}
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+#endif
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static int __init bf609_init_pm(void)
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{
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int irq;
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int error;
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-#if CONFIG_PM_BFIN_WAKE_PE12
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+#ifdef CONFIG_PM_BFIN_WAKE_PE12
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irq = gpio_to_irq(GPIO_PE12);
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if (irq < 0) {
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error = irq;
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