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@@ -71,53 +71,50 @@ static void pbus_assign_resources_sorted(const struct pci_bus *bus)
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void pci_setup_cardbus(struct pci_bus *bus)
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void pci_setup_cardbus(struct pci_bus *bus)
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{
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{
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struct pci_dev *bridge = bus->self;
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struct pci_dev *bridge = bus->self;
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+ struct resource *res;
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struct pci_bus_region region;
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struct pci_bus_region region;
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dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
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dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
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pci_domain_nr(bus), bus->number);
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pci_domain_nr(bus), bus->number);
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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- if (bus->resource[0]->flags & IORESOURCE_IO) {
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+ res = bus->resource[0];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_IO) {
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/*
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/*
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* The IO resource is allocated a range twice as large as it
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* The IO resource is allocated a range twice as large as it
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* would normally need. This allows us to set both IO regs.
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* would normally need. This allows us to set both IO regs.
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*/
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*/
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- dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
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- (unsigned long)region.start,
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- (unsigned long)region.end);
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
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region.start);
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region.start);
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pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
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pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
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region.end);
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region.end);
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}
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}
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
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- if (bus->resource[1]->flags & IORESOURCE_IO) {
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- dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
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- (unsigned long)region.start,
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- (unsigned long)region.end);
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+ res = bus->resource[1];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_IO) {
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
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pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
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region.start);
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region.start);
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pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
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pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
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region.end);
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region.end);
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}
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}
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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- if (bus->resource[2]->flags & IORESOURCE_MEM) {
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- dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
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- (unsigned long)region.start,
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- (unsigned long)region.end);
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+ res = bus->resource[2];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_MEM) {
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
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region.start);
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region.start);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
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pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
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region.end);
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region.end);
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}
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}
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
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- if (bus->resource[3]->flags & IORESOURCE_MEM) {
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- dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
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- (unsigned long)region.start,
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- (unsigned long)region.end);
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+ res = bus->resource[3];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_MEM) {
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
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pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
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region.start);
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region.start);
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pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
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pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
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@@ -140,6 +137,7 @@ EXPORT_SYMBOL(pci_setup_cardbus);
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static void pci_setup_bridge(struct pci_bus *bus)
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static void pci_setup_bridge(struct pci_bus *bus)
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{
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{
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struct pci_dev *bridge = bus->self;
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struct pci_dev *bridge = bus->self;
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+ struct resource *res;
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struct pci_bus_region region;
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struct pci_bus_region region;
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u32 l, bu, lu, io_upper16;
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u32 l, bu, lu, io_upper16;
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int pref_mem64;
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int pref_mem64;
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@@ -151,23 +149,22 @@ static void pci_setup_bridge(struct pci_bus *bus)
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pci_domain_nr(bus), bus->number);
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pci_domain_nr(bus), bus->number);
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/* Set up the top and bottom of the PCI I/O segment for this bus. */
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/* Set up the top and bottom of the PCI I/O segment for this bus. */
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
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- if (bus->resource[0]->flags & IORESOURCE_IO) {
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+ res = bus->resource[0];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_IO) {
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pci_read_config_dword(bridge, PCI_IO_BASE, &l);
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pci_read_config_dword(bridge, PCI_IO_BASE, &l);
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l &= 0xffff0000;
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l &= 0xffff0000;
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l |= (region.start >> 8) & 0x00f0;
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l |= (region.start >> 8) & 0x00f0;
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l |= region.end & 0xf000;
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l |= region.end & 0xf000;
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/* Set up upper 16 bits of I/O base/limit. */
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/* Set up upper 16 bits of I/O base/limit. */
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io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
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io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
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- dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n",
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- (unsigned long)region.start,
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- (unsigned long)region.end);
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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}
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}
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else {
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else {
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/* Clear upper 16 bits of I/O base/limit. */
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/* Clear upper 16 bits of I/O base/limit. */
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io_upper16 = 0;
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io_upper16 = 0;
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l = 0x00f0;
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l = 0x00f0;
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- dev_info(&bridge->dev, " IO window: disabled\n");
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+ dev_info(&bridge->dev, " bridge window [io disabled]\n");
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}
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}
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/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
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/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
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pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
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pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
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@@ -178,17 +175,16 @@ static void pci_setup_bridge(struct pci_bus *bus)
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/* Set up the top and bottom of the PCI Memory segment
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/* Set up the top and bottom of the PCI Memory segment
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for this bus. */
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for this bus. */
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
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- if (bus->resource[1]->flags & IORESOURCE_MEM) {
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+ res = bus->resource[1];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_MEM) {
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l = (region.start >> 16) & 0xfff0;
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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l |= region.end & 0xfff00000;
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- dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
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- (unsigned long)region.start,
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- (unsigned long)region.end);
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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}
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}
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else {
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else {
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l = 0x0000fff0;
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l = 0x0000fff0;
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- dev_info(&bridge->dev, " MEM window: disabled\n");
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+ dev_info(&bridge->dev, " bridge window [mem disabled]\n");
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}
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}
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pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
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pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
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@@ -200,24 +196,21 @@ static void pci_setup_bridge(struct pci_bus *bus)
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/* Set up PREF base/limit. */
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/* Set up PREF base/limit. */
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pref_mem64 = 0;
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pref_mem64 = 0;
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bu = lu = 0;
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bu = lu = 0;
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- pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
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- if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
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- int width = 8;
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+ res = bus->resource[2];
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+ pcibios_resource_to_bus(bridge, ®ion, res);
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+ if (res->flags & IORESOURCE_PREFETCH) {
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l = (region.start >> 16) & 0xfff0;
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l = (region.start >> 16) & 0xfff0;
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l |= region.end & 0xfff00000;
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l |= region.end & 0xfff00000;
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- if (bus->resource[2]->flags & IORESOURCE_MEM_64) {
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+ if (res->flags & IORESOURCE_MEM_64) {
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pref_mem64 = 1;
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pref_mem64 = 1;
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bu = upper_32_bits(region.start);
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bu = upper_32_bits(region.start);
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lu = upper_32_bits(region.end);
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lu = upper_32_bits(region.end);
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- width = 16;
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}
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}
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- dev_info(&bridge->dev, " PREFETCH window: %#0*llx-%#0*llx\n",
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- width, (unsigned long long)region.start,
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- width, (unsigned long long)region.end);
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+ dev_info(&bridge->dev, " bridge window %pR\n", res);
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}
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}
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else {
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else {
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l = 0x0000fff0;
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l = 0x0000fff0;
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- dev_info(&bridge->dev, " PREFETCH window: disabled\n");
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+ dev_info(&bridge->dev, " bridge window [mem pref disabled]\n");
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}
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}
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
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@@ -391,7 +384,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
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order = __ffs(align) - 20;
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order = __ffs(align) - 20;
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if (order > 11) {
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if (order > 11) {
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dev_warn(&dev->dev, "BAR %d: bad alignment %llx: "
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dev_warn(&dev->dev, "BAR %d: bad alignment %llx: "
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- "%pRt\n", i, (unsigned long long)align, r);
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+ "%pR\n", i, (unsigned long long)align, r);
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r->flags = 0;
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r->flags = 0;
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continue;
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continue;
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}
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}
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@@ -582,7 +575,7 @@ static void pci_bus_dump_res(struct pci_bus *bus)
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if (!res || !res->end)
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if (!res || !res->end)
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continue;
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continue;
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- dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pRt\n", i, res);
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+ dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
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}
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}
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}
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}
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