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@@ -597,26 +597,6 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
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/* Get the default CCTL */
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cctl = txd->cctl;
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- /*
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- * On the PL080 we have two bus masters and we
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- * should select one for source and one for
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- * destination. We try to use AHB2 for the
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- * bus which does not increment (typically the
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- * peripheral) else we just choose something.
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- */
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- cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
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- if (pl08x->vd->dualmaster) {
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- if (cctl & PL080_CONTROL_SRC_INCR)
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- /* Source increments, use AHB2 for destination */
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- cctl |= PL080_CONTROL_DST_AHB2;
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- else if (cctl & PL080_CONTROL_DST_INCR)
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- /* Destination increments, use AHB2 for source */
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- cctl |= PL080_CONTROL_SRC_AHB2;
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- else
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- /* Just pick something, source AHB1 dest AHB2 */
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- cctl |= PL080_CONTROL_DST_AHB2;
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- }
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-
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/* Find maximum width of the source bus */
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txd->srcbus.maxwidth =
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pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
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@@ -1340,14 +1320,25 @@ static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
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txd->direction = DMA_NONE;
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txd->srcbus.addr = src;
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txd->dstbus.addr = dest;
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+ txd->len = len;
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/* Set platform data for m2m */
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txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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- txd->cctl = pl08x->pd->memcpy_channel.cctl;
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+ txd->cctl = pl08x->pd->memcpy_channel.cctl &
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+ ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
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/* Both to be incremented or the code will break */
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txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
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- txd->len = len;
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+
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+ /*
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+ * On the PL080 we have two bus masters and we should select one for
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+ * source and one for destination. We try to use AHB2 for the bus
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+ * which does not increment (typically the peripheral) else we just
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+ * choose something.
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+ */
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+ if (pl08x->vd->dualmaster)
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+ /* Source increments, use AHB2 for destination */
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+ txd->cctl |= PL080_CONTROL_DST_AHB2;
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ret = pl08x_prep_channel_resources(plchan, txd);
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if (ret)
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@@ -1399,8 +1390,11 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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* channel target address dynamically at runtime.
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*/
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txd->direction = direction;
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+ txd->len = sgl->length;
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+
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txd->cctl = plchan->cd->cctl &
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- ~(PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
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+ ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
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+ PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
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PL080_CONTROL_PROT_MASK);
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/* Access the cell in privileged mode, non-bufferable, non-cacheable */
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@@ -1409,6 +1403,9 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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if (direction == DMA_TO_DEVICE) {
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txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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txd->cctl |= PL080_CONTROL_SRC_INCR;
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+ if (pl08x->vd->dualmaster)
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+ /* Source increments, use AHB2 for destination */
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+ txd->cctl |= PL080_CONTROL_DST_AHB2;
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txd->srcbus.addr = sgl->dma_address;
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if (plchan->runtime_addr)
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txd->dstbus.addr = plchan->runtime_addr;
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@@ -1417,6 +1414,9 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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} else if (direction == DMA_FROM_DEVICE) {
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txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
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txd->cctl |= PL080_CONTROL_DST_INCR;
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+ if (pl08x->vd->dualmaster)
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+ /* Destination increments, use AHB2 for source */
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+ txd->cctl |= PL080_CONTROL_SRC_AHB2;
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if (plchan->runtime_addr)
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txd->srcbus.addr = plchan->runtime_addr;
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else
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@@ -1427,7 +1427,6 @@ static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
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"%s direction unsupported\n", __func__);
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return NULL;
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}
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- txd->len = sgl->length;
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ret = pl08x_prep_channel_resources(plchan, txd);
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if (ret)
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