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@@ -1,6 +1,6 @@
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-/* -*- c-basic-offset: 8 -*-
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+/*
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+ * Driver for OHCI 1394 controllers
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*
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- * fw-ohci.c - Driver for OHCI 1394 boards
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* Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
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*
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* This program is free software; you can redistribute it and/or modify
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@@ -141,8 +141,10 @@ struct fw_ohci {
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int request_generation;
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u32 bus_seconds;
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- /* Spinlock for accessing fw_ohci data. Never call out of
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- * this driver with this lock held. */
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+ /*
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+ * Spinlock for accessing fw_ohci data. Never call out of
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+ * this driver with this lock held.
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+ */
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spinlock_t lock;
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u32 self_id_buffer[512];
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@@ -328,13 +330,15 @@ static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
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p.timestamp = status & 0xffff;
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p.generation = ohci->request_generation;
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- /* The OHCI bus reset handler synthesizes a phy packet with
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+ /*
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+ * The OHCI bus reset handler synthesizes a phy packet with
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* the new generation number when a bus reset happens (see
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* section 8.4.2.3). This helps us determine when a request
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* was received and make sure we send the response in the same
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* generation. We only need this for requests; for responses
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* we use the unique tlabel for finding the matching
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- * request. */
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+ * request.
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+ */
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if (p.ack + 16 == 0x09)
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ohci->request_generation = (buffer[2] >> 16) & 0xff;
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@@ -360,9 +364,11 @@ static void ar_context_tasklet(unsigned long data)
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if (d->res_count == 0) {
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size_t size, rest, offset;
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- /* This descriptor is finished and we may have a
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+ /*
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+ * This descriptor is finished and we may have a
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* packet split across this and the next buffer. We
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- * reuse the page for reassembling the split packet. */
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+ * reuse the page for reassembling the split packet.
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+ */
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offset = offsetof(struct ar_buffer, data);
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dma_unmap_single(ohci->card.device,
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@@ -473,11 +479,13 @@ context_init(struct context *ctx, struct fw_ohci *ohci,
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ctx->tail_descriptor = ctx->buffer;
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ctx->tail_descriptor_last = ctx->buffer;
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- /* We put a dummy descriptor in the buffer that has a NULL
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+ /*
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+ * We put a dummy descriptor in the buffer that has a NULL
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* branch address and looks like it's been sent. That way we
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* have a descriptor to append DMA programs to. Also, the
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* ring buffer invariant is that it always has at least one
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- * element so that head == tail means buffer full. */
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+ * element so that head == tail means buffer full.
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+ */
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memset(ctx->head_descriptor, 0, sizeof *ctx->head_descriptor);
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ctx->head_descriptor->control = cpu_to_le16(descriptor_output_last);
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@@ -575,9 +583,11 @@ struct driver_data {
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struct fw_packet *packet;
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};
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-/* This function apppends a packet to the DMA queue for transmission.
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+/*
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+ * This function apppends a packet to the DMA queue for transmission.
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* Must always be called with the ochi->lock held to ensure proper
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- * generation handling and locking around packet queue manipulation. */
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+ * generation handling and locking around packet queue manipulation.
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+ */
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static int
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at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
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{
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@@ -598,10 +608,12 @@ at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
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d[0].control = cpu_to_le16(descriptor_key_immediate);
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d[0].res_count = cpu_to_le16(packet->timestamp);
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- /* The DMA format for asyncronous link packets is different
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+ /*
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+ * The DMA format for asyncronous link packets is different
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* from the IEEE1394 layout, so shift the fields around
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* accordingly. If header_length is 8, it's a PHY packet, to
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- * which we need to prepend an extra quadlet. */
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+ * which we need to prepend an extra quadlet.
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+ */
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header = (__le32 *) &d[1];
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if (packet->header_length > 8) {
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@@ -703,14 +715,18 @@ static int handle_at_packet(struct context *context,
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break;
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case OHCI1394_evt_flushed:
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- /* The packet was flushed should give same error as
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- * when we try to use a stale generation count. */
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+ /*
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+ * The packet was flushed should give same error as
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+ * when we try to use a stale generation count.
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+ */
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packet->ack = RCODE_GENERATION;
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break;
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case OHCI1394_evt_missing_ack:
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- /* Using a valid (current) generation count, but the
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- * node is not on the bus or not sending acks. */
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+ /*
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+ * Using a valid (current) generation count, but the
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+ * node is not on the bus or not sending acks.
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+ */
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packet->ack = RCODE_NO_ACK;
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break;
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@@ -887,10 +903,12 @@ static void bus_reset_tasklet(unsigned long data)
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}
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ohci->node_id = reg & 0xffff;
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- /* The count in the SelfIDCount register is the number of
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+ /*
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+ * The count in the SelfIDCount register is the number of
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* bytes in the self ID receive buffer. Since we also receive
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* the inverted quadlets and a header quadlet, we shift one
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- * bit extra to get the actual number of self IDs. */
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+ * bit extra to get the actual number of self IDs.
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+ */
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self_id_count = (reg_read(ohci, OHCI1394_SelfIDCount) >> 3) & 0x3ff;
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generation = (le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
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@@ -901,7 +919,8 @@ static void bus_reset_tasklet(unsigned long data)
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ohci->self_id_buffer[j] = le32_to_cpu(ohci->self_id_cpu[i]);
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}
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- /* Check the consistency of the self IDs we just read. The
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+ /*
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+ * Check the consistency of the self IDs we just read. The
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* problem we face is that a new bus reset can start while we
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* read out the self IDs from the DMA buffer. If this happens,
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* the DMA buffer will be overwritten with new self IDs and we
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@@ -911,7 +930,8 @@ static void bus_reset_tasklet(unsigned long data)
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* self IDs in the buffer before reading them out and compare
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* it to the current generation after reading them out. If
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* the two generations match we know we have a consistent set
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- * of self IDs. */
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+ * of self IDs.
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+ */
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new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
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if (new_generation != generation) {
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@@ -928,12 +948,14 @@ static void bus_reset_tasklet(unsigned long data)
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context_stop(&ohci->at_response_ctx);
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reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
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- /* This next bit is unrelated to the AT context stuff but we
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+ /*
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+ * This next bit is unrelated to the AT context stuff but we
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* have to do it under the spinlock also. If a new config rom
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* was set up before this reset, the old one is now no longer
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* in use and we can free it. Update the config rom pointers
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* to point to the current config rom and clear the
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- * next_config_rom pointer so a new udpate can take place. */
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+ * next_config_rom pointer so a new udpate can take place.
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+ */
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if (ohci->next_config_rom != NULL) {
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dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
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@@ -942,10 +964,12 @@ static void bus_reset_tasklet(unsigned long data)
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ohci->config_rom_bus = ohci->next_config_rom_bus;
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ohci->next_config_rom = NULL;
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- /* Restore config_rom image and manually update
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+ /*
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+ * Restore config_rom image and manually update
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* config_rom registers. Writing the header quadlet
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* will indicate that the config rom is ready, so we
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- * do that last. */
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+ * do that last.
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+ */
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reg_write(ohci, OHCI1394_BusOptions,
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be32_to_cpu(ohci->config_rom[2]));
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ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
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@@ -1018,7 +1042,8 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
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struct fw_ohci *ohci = fw_ohci(card);
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struct pci_dev *dev = to_pci_dev(card->device);
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- /* When the link is not yet enabled, the atomic config rom
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+ /*
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+ * When the link is not yet enabled, the atomic config rom
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* update mechanism described below in ohci_set_config_rom()
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* is not active. We have to update ConfigRomHeader and
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* BusOptions manually, and the write to ConfigROMmap takes
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@@ -1067,8 +1092,10 @@ static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
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OHCI1394_HCControl_BIBimageValid);
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flush_writes(ohci);
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- /* We are ready to go, initiate bus reset to finish the
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- * initialization. */
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+ /*
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+ * We are ready to go, initiate bus reset to finish the
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+ * initialization.
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+ */
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fw_core_initiate_bus_reset(&ohci->card, 1);
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@@ -1086,7 +1113,8 @@ ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
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ohci = fw_ohci(card);
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- /* When the OHCI controller is enabled, the config rom update
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+ /*
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+ * When the OHCI controller is enabled, the config rom update
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* mechanism is a bit tricky, but easy enough to use. See
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* section 5.5.6 in the OHCI specification.
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*
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@@ -1141,11 +1169,13 @@ ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
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spin_unlock_irqrestore(&ohci->lock, flags);
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- /* Now initiate a bus reset to have the changes take
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+ /*
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+ * Now initiate a bus reset to have the changes take
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* effect. We clean up the old config rom memory and DMA
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* mappings in the bus reset tasklet, since the OHCI
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* controller could need to access it before the bus reset
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- * takes effect. */
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+ * takes effect.
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+ */
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if (retval == 0)
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fw_core_initiate_bus_reset(&ohci->card, 1);
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@@ -1196,8 +1226,10 @@ ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
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unsigned long flags;
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int n, retval = 0;
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- /* FIXME: Make sure this bitmask is cleared when we clear the busReset
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- * interrupt bit. Clear physReqResourceAllBuses on bus reset. */
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+ /*
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+ * FIXME: Make sure this bitmask is cleared when we clear the busReset
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+ * interrupt bit. Clear physReqResourceAllBuses on bus reset.
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+ */
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spin_lock_irqsave(&ohci->lock, flags);
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@@ -1206,8 +1238,10 @@ ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
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goto out;
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}
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- /* NOTE, if the node ID contains a non-local bus ID, physical DMA is
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- * enabled for _all_ nodes on remote buses. */
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+ /*
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+ * Note, if the node ID contains a non-local bus ID, physical DMA is
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+ * enabled for _all_ nodes on remote buses.
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+ */
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n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
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if (n < 32)
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@@ -1257,11 +1291,13 @@ static int handle_ir_dualbuffer_packet(struct context *context,
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p = db + 1;
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end = p + header_length;
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while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
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- /* The iso header is byteswapped to little endian by
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+ /*
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+ * The iso header is byteswapped to little endian by
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* the controller, but the remaining header quadlets
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* are big endian. We want to present all the headers
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* as big endian, so we have to swap the first
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- * quadlet. */
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+ * quadlet.
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+ */
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*(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
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memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
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i += ctx->base.header_size;
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@@ -1457,8 +1493,10 @@ ohci_queue_iso_transmit(struct fw_iso_context *base,
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u32 payload_index, payload_end_index, next_page_index;
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int page, end_page, i, length, offset;
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- /* FIXME: Cycle lost behavior should be configurable: lose
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- * packet, retransmit or terminate.. */
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+ /*
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+ * FIXME: Cycle lost behavior should be configurable: lose
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+ * packet, retransmit or terminate..
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+ */
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p = packet;
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payload_index = payload;
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@@ -1553,8 +1591,10 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
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u32 z, header_z, length, rest;
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int page, offset, packet_count, header_size;
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- /* FIXME: Cycle lost behavior should be configurable: lose
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- * packet, retransmit or terminate.. */
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+ /*
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+ * FIXME: Cycle lost behavior should be configurable: lose
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+ * packet, retransmit or terminate..
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+ */
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if (packet->skip) {
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d = context_get_descriptors(&ctx->context, 2, &d_bus);
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@@ -1572,8 +1612,10 @@ ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
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p = packet;
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z = 2;
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- /* The OHCI controller puts the status word in the header
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- * buffer too, so we need 4 extra bytes per packet. */
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+ /*
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+ * The OHCI controller puts the status word in the header
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+ * buffer too, so we need 4 extra bytes per packet.
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+ */
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packet_count = p->header_length / ctx->base.header_size;
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header_size = packet_count * (ctx->base.header_size + 4);
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@@ -1673,8 +1715,6 @@ static int software_reset(struct fw_ohci *ohci)
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return -EBUSY;
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}
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-/* ---------- pci subsystem interface ---------- */
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-
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enum {
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CLEANUP_SELF_ID,
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CLEANUP_REGISTERS,
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@@ -1753,11 +1793,13 @@ pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
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return cleanup(ohci, CLEANUP_REGISTERS, -EBUSY);
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}
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- /* Now enable LPS, which we need in order to start accessing
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+ /*
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+ * Now enable LPS, which we need in order to start accessing
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* most of the registers. In fact, on some cards (ALI M5251),
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* accessing registers in the SClk domain without LPS enabled
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* will lock up the machine. Wait 50msec to make sure we have
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- * full link enabled. */
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+ * full link enabled.
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+ */
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reg_write(ohci, OHCI1394_HCControlSet,
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OHCI1394_HCControl_LPS |
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OHCI1394_HCControl_postedWriteEnable);
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@@ -1854,8 +1896,10 @@ static void pci_remove(struct pci_dev *dev)
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flush_writes(ohci);
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fw_core_remove_card(&ohci->card);
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- /* FIXME: Fail all pending packets here, now that the upper
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- * layers can't queue any more. */
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+ /*
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+ * FIXME: Fail all pending packets here, now that the upper
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+ * layers can't queue any more.
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+ */
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software_reset(ohci);
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free_irq(dev->irq, ohci);
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