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@@ -8,8 +8,8 @@
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* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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*/
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-#ifndef __ASM_IA64_UV_MMRS__
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-#define __ASM_IA64_UV_MMRS__
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+#ifndef _ASM_IA64_UV_UV_MMRS_H
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+#define _ASM_IA64_UV_UV_MMRS_H
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#define UV_MMR_ENABLE (1UL << 63)
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@@ -242,6 +242,158 @@ union uvh_event_occurred0_u {
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#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
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#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
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+/* ========================================================================= */
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+/* UVH_GR0_TLB_INT0_CONFIG */
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+/* ========================================================================= */
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+#define UVH_GR0_TLB_INT0_CONFIG 0x61b00UL
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+
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+#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0
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+#define UVH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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+#define UVH_GR0_TLB_INT0_CONFIG_DM_SHFT 8
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+#define UVH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
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+#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11
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+#define UVH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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+#define UVH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12
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+#define UVH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
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+#define UVH_GR0_TLB_INT0_CONFIG_P_SHFT 13
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+#define UVH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
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+#define UVH_GR0_TLB_INT0_CONFIG_T_SHFT 15
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+#define UVH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
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+#define UVH_GR0_TLB_INT0_CONFIG_M_SHFT 16
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+#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
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+#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32
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+#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
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+
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+union uvh_gr0_tlb_int0_config_u {
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+ unsigned long v;
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+ struct uvh_gr0_tlb_int0_config_s {
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+ unsigned long vector_ : 8; /* RW */
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+ unsigned long dm : 3; /* RW */
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+ unsigned long destmode : 1; /* RW */
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+ unsigned long status : 1; /* RO */
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+ unsigned long p : 1; /* RO */
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+ unsigned long rsvd_14 : 1; /* */
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+ unsigned long t : 1; /* RO */
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+ unsigned long m : 1; /* RW */
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+ unsigned long rsvd_17_31: 15; /* */
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+ unsigned long apic_id : 32; /* RW */
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+ } s;
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+};
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+
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+/* ========================================================================= */
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+/* UVH_GR0_TLB_INT1_CONFIG */
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+/* ========================================================================= */
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+#define UVH_GR0_TLB_INT1_CONFIG 0x61b40UL
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+
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+#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0
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+#define UVH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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+#define UVH_GR0_TLB_INT1_CONFIG_DM_SHFT 8
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+#define UVH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
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+#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11
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+#define UVH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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+#define UVH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12
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+#define UVH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
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+#define UVH_GR0_TLB_INT1_CONFIG_P_SHFT 13
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+#define UVH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
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+#define UVH_GR0_TLB_INT1_CONFIG_T_SHFT 15
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+#define UVH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
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+#define UVH_GR0_TLB_INT1_CONFIG_M_SHFT 16
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+#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
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+#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32
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+#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
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+
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+union uvh_gr0_tlb_int1_config_u {
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+ unsigned long v;
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+ struct uvh_gr0_tlb_int1_config_s {
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+ unsigned long vector_ : 8; /* RW */
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+ unsigned long dm : 3; /* RW */
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+ unsigned long destmode : 1; /* RW */
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+ unsigned long status : 1; /* RO */
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+ unsigned long p : 1; /* RO */
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+ unsigned long rsvd_14 : 1; /* */
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+ unsigned long t : 1; /* RO */
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+ unsigned long m : 1; /* RW */
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+ unsigned long rsvd_17_31: 15; /* */
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+ unsigned long apic_id : 32; /* RW */
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+ } s;
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+};
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+
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+/* ========================================================================= */
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+/* UVH_GR1_TLB_INT0_CONFIG */
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+/* ========================================================================= */
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+#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL
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+
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+#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
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+#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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+#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
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+#define UVH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL
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+#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11
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+#define UVH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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+#define UVH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12
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+#define UVH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
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+#define UVH_GR1_TLB_INT0_CONFIG_P_SHFT 13
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+#define UVH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL
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+#define UVH_GR1_TLB_INT0_CONFIG_T_SHFT 15
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+#define UVH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL
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+#define UVH_GR1_TLB_INT0_CONFIG_M_SHFT 16
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+#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
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+#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32
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+#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
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+
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+union uvh_gr1_tlb_int0_config_u {
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+ unsigned long v;
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+ struct uvh_gr1_tlb_int0_config_s {
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+ unsigned long vector_ : 8; /* RW */
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+ unsigned long dm : 3; /* RW */
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+ unsigned long destmode : 1; /* RW */
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+ unsigned long status : 1; /* RO */
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+ unsigned long p : 1; /* RO */
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+ unsigned long rsvd_14 : 1; /* */
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+ unsigned long t : 1; /* RO */
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+ unsigned long m : 1; /* RW */
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+ unsigned long rsvd_17_31: 15; /* */
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+ unsigned long apic_id : 32; /* RW */
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+ } s;
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+};
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+
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+/* ========================================================================= */
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+/* UVH_GR1_TLB_INT1_CONFIG */
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+/* ========================================================================= */
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+#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL
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+
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+#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
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+#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL
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+#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
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+#define UVH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL
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+#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11
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+#define UVH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL
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+#define UVH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12
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+#define UVH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL
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+#define UVH_GR1_TLB_INT1_CONFIG_P_SHFT 13
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+#define UVH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL
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+#define UVH_GR1_TLB_INT1_CONFIG_T_SHFT 15
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+#define UVH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL
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+#define UVH_GR1_TLB_INT1_CONFIG_M_SHFT 16
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+#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
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+#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32
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+#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
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+
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+union uvh_gr1_tlb_int1_config_u {
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+ unsigned long v;
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+ struct uvh_gr1_tlb_int1_config_s {
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+ unsigned long vector_ : 8; /* RW */
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+ unsigned long dm : 3; /* RW */
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+ unsigned long destmode : 1; /* RW */
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+ unsigned long status : 1; /* RO */
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+ unsigned long p : 1; /* RO */
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+ unsigned long rsvd_14 : 1; /* */
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+ unsigned long t : 1; /* RO */
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+ unsigned long m : 1; /* RW */
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+ unsigned long rsvd_17_31: 15; /* */
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+ unsigned long apic_id : 32; /* RW */
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+ } s;
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+};
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+
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/* ========================================================================= */
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/* UVH_INT_CMPB */
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/* ========================================================================= */
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@@ -670,4 +822,4 @@ union uvh_si_alias2_overlay_config_u {
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};
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-#endif /* __ASM_IA64_UV_MMRS__ */
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+#endif /* _ASM_IA64_UV_UV_MMRS_H */
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