|
@@ -11,25 +11,23 @@
|
|
|
* Force strict CPU ordering.
|
|
|
* And yes, this is required on UP too when we're talking
|
|
|
* to devices.
|
|
|
- *
|
|
|
- * This is very similar to the ppc eieio/sync instruction in that is
|
|
|
- * does a checkpoint syncronisation & makes sure that
|
|
|
- * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
|
|
|
*/
|
|
|
|
|
|
-#define eieio() asm volatile("bcr 15,0" : : : "memory")
|
|
|
-#define SYNC_OTHER_CORES(x) eieio()
|
|
|
-#define mb() eieio()
|
|
|
-#define rmb() eieio()
|
|
|
-#define wmb() eieio()
|
|
|
-#define read_barrier_depends() do { } while(0)
|
|
|
-#define smp_mb() mb()
|
|
|
-#define smp_rmb() rmb()
|
|
|
-#define smp_wmb() wmb()
|
|
|
-#define smp_read_barrier_depends() read_barrier_depends()
|
|
|
-#define smp_mb__before_clear_bit() smp_mb()
|
|
|
-#define smp_mb__after_clear_bit() smp_mb()
|
|
|
+static inline void mb(void)
|
|
|
+{
|
|
|
+ asm volatile("bcr 15,0" : : : "memory");
|
|
|
+}
|
|
|
+
|
|
|
+#define rmb() mb()
|
|
|
+#define wmb() mb()
|
|
|
+#define read_barrier_depends() do { } while(0)
|
|
|
+#define smp_mb() mb()
|
|
|
+#define smp_rmb() rmb()
|
|
|
+#define smp_wmb() wmb()
|
|
|
+#define smp_read_barrier_depends() read_barrier_depends()
|
|
|
+#define smp_mb__before_clear_bit() smp_mb()
|
|
|
+#define smp_mb__after_clear_bit() smp_mb()
|
|
|
|
|
|
-#define set_mb(var, value) do { var = value; mb(); } while (0)
|
|
|
+#define set_mb(var, value) do { var = value; mb(); } while (0)
|
|
|
|
|
|
#endif /* __ASM_BARRIER_H */
|