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@@ -559,6 +559,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
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unsigned long last_page = 0;
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u32 reg;
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enum edac_type mode;
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+ enum mem_type mtype;
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pci_read_config_dword(pvt->pci_br, SAD_TARGET, ®);
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pvt->sbridge_dev->source_id = SOURCE_ID(reg);
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@@ -601,10 +602,10 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
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if (IS_RDIMM_ENABLED(reg)) {
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/* FIXME: Can also be LRDIMM */
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debugf0("Memory is registered\n");
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- mode = MEM_RDDR3;
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+ mtype = MEM_RDDR3;
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} else {
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debugf0("Memory is unregistered\n");
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- mode = MEM_DDR3;
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+ mtype = MEM_DDR3;
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}
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/* On all supported DDR3 DIMM types, there are 8 banks available */
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@@ -643,7 +644,7 @@ static int get_dimm_config(const struct mem_ctl_info *mci)
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csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
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csr->ce_count = 0;
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csr->ue_count = 0;
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- csr->mtype = mode;
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+ csr->mtype = mtype;
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csr->edac_mode = mode;
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csr->nr_channels = 1;
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csr->channels[0].chan_idx = i;
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