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@@ -29,21 +29,14 @@ typedef enum _VERSION_8192S{
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VERSION_8192S_CCUT
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}VERSION_8192S,*PVERSION_8192S;
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-//#ifdef RTL8192SU
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typedef enum _VERSION_8192SUsb{
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VERSION_8192SU_A, //A-Cut
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VERSION_8192SU_B, //B-Cut
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VERSION_8192SU_C, //C-Cut
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}VERSION_8192SUsb, *PVERSION_8192SUsb;
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-//#else
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-typedef enum _VERSION_819xU{
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- VERSION_819xU_A, // A-cut
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- VERSION_819xU_B, // B-cut
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- VERSION_819xU_C,// C-cut
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-}VERSION_819xU,*PVERSION_819xU;
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-//#endif
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-
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-/* 2007/11/15 MH Define different RF type. */
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+
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+
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+/* RF type. */
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typedef enum _RT_RF_TYPE_DEFINITION
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{
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RF_1T2R = 0,
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@@ -51,9 +44,6 @@ typedef enum _RT_RF_TYPE_DEFINITION
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RF_2T2R,
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RF_1T1R,
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RF_2T2R_GREEN,
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- //RF_3T3R,
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- //RF_3T4R,
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- //RF_4T4R,
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RF_819X_MAX_TYPE
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}RT_RF_TYPE_DEF_E;
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@@ -71,8 +61,6 @@ typedef enum _BaseBand_Config_Type{
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#define MAX_RX_URB 16
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#define R8180_MAX_RETRY 255
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-//#define MAX_RX_NORMAL_URB 3
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-//#define MAX_RX_COMMAND_URB 2
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#define RX_URB_SIZE 9100
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#define BB_ANTATTEN_CHAN14 0x0c
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@@ -147,13 +135,6 @@ typedef enum _BaseBand_Config_Type{
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#define EPROM_W_SHIFT 1
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#define EPROM_R_SHIFT 0
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-//#define MAC0 0x000,
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-//#define MAC1 0x001,
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-//#define MAC2 0x002,
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-//#define MAC3 0x003,
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-//#define MAC4 0x004,
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-//#define MAC5 0x005,
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-
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//============================================================
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// 8192S Regsiter offset definition
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//============================================================
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@@ -529,14 +510,6 @@ typedef enum _BaseBand_Config_Type{
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// USB RPWM register
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#define USB_RPWM 0xFE58
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-//FIXLZM SVN_BRACH NOT MOD HERE, IF MOD RX IS LITTLE LOW
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-//#if ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==PCI_INTERFACE))
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-//#define RPWM PCI_RPWM
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-//#elif ((HAL_CODE_BASE == RTL8192_S) && (DEV_BUS_TYPE==USB_INTERFACE))
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-//#define RPWM USB_RPWM
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-//#endif
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-
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-
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//============================================================================
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// 8190 Regsiter offset definition
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//============================================================================
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@@ -777,13 +750,11 @@ typedef enum _BaseBand_Config_Type{
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#define RCR_MXDMA_OFFSET 8
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#define RCR_FIFO_OFFSET 13
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-//in 92U FIXLZM
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-//#ifdef RTL8192U
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#define RCR_ONLYERLPKT BIT31 // Early Receiving based on Packet Size.
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#define RCR_ENCS2 BIT30 // Enable Carrier Sense Detection Method 2
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#define RCR_ENCS1 BIT29 // Enable Carrier Sense Detection Method 1
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#define RCR_ACKTXBW (BIT24|BIT25) // TXBW Setting of ACK frames
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-//#endif
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+
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//----------------------------------------------------------------------------
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// 8192S (MSR) Media Status Register (Offset 0x4C, 8 bits)
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//----------------------------------------------------------------------------
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@@ -1460,34 +1431,4 @@ Default: 00b.
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#define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
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#define HAL_8192S_HW_GPIO_WPS_BIT BIT4
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-#endif //R8192S_HW
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+#endif
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Florian Schilhabel