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[ARM] 5412/1: XSCALE: add ice dcc support

SCALE: add ice dcc support

Tested on the ixp425 with the ice PEEDI

Ack-by: Eric Miao <eric.miao@marvell.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Jean-Christop PLAGNIOL-VILLARD 16 年之前
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共有 4 个文件被更改,包括 49 次插入1 次删除
  1. 1 1
      arch/arm/Kconfig.debug
  2. 6 0
      arch/arm/boot/compressed/head.S
  3. 15 0
      arch/arm/boot/compressed/misc.c
  4. 27 0
      arch/arm/kernel/debug.S

+ 1 - 1
arch/arm/Kconfig.debug

@@ -77,7 +77,7 @@ config DEBUG_ICEDCC
 	  Say Y here if you want the debug print routines to direct their
 	  Say Y here if you want the debug print routines to direct their
 	  output to the EmbeddedICE macrocell's DCC channel using
 	  output to the EmbeddedICE macrocell's DCC channel using
 	  co-processor 14. This is known to work on the ARM9 style ICE
 	  co-processor 14. This is known to work on the ARM9 style ICE
-	  channel.
+	  channel and on the XScale with the PEEDI.
 
 
 	  It does include a timeout to ensure that the system does not
 	  It does include a timeout to ensure that the system does not
 	  totally freeze when there is nothing connected to read.
 	  totally freeze when there is nothing connected to read.

+ 6 - 0
arch/arm/boot/compressed/head.S

@@ -27,6 +27,12 @@
 		.macro	writeb, ch, rb
 		.macro	writeb, ch, rb
 		mcr	p14, 0, \ch, c0, c5, 0
 		mcr	p14, 0, \ch, c0, c5, 0
 		.endm
 		.endm
+#elif defined(CONFIG_CPU_XSCALE)
+		.macro	loadsp, rb
+		.endm
+		.macro	writeb, ch, rb
+		mcr	p14, 0, \ch, c8, c0, 0
+		.endm
 #else
 #else
 		.macro	loadsp, rb
 		.macro	loadsp, rb
 		.endm
 		.endm

+ 15 - 0
arch/arm/boot/compressed/misc.c

@@ -46,6 +46,21 @@ static void icedcc_putc(int ch)
 
 
 	asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
 	asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch));
 }
 }
+#elif defined(CONFIG_CPU_XSCALE)
+
+static void icedcc_putc(int ch)
+{
+	int status, i = 0x4000000;
+
+	do {
+		if (--i < 0)
+			return;
+
+		asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status));
+	} while (status & (1 << 28));
+
+	asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch));
+}
 
 
 #else
 #else
 
 

+ 27 - 0
arch/arm/kernel/debug.S

@@ -49,6 +49,33 @@
 1002:
 1002:
 		.endm
 		.endm
 
 
+#elif defined(CONFIG_CPU_XSCALE)
+
+		.macro	addruart, rx
+		.endm
+
+		.macro	senduart, rd, rx
+		mcr	p14, 0, \rd, c8, c0, 0
+		.endm
+
+		.macro	busyuart, rd, rx
+1001:
+		mrc	p14, 0, \rx, c14, c0, 0
+		tst	\rx, #0x10000000
+		beq	1001b
+		.endm
+
+		.macro	waituart, rd, rx
+		mov	\rd, #0x10000000
+1001:
+		subs	\rd, \rd, #1
+		bmi	1002f
+		mrc	p14, 0, \rx, c14, c0, 0
+		tst	\rx, #0x10000000
+		bne	1001b
+1002:
+		.endm
+
 #else
 #else
 
 
 		.macro	addruart, rx
 		.macro	addruart, rx