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@@ -551,6 +551,7 @@ union ring_type {
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#define PHY_OUI_MARVELL 0x5043
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#define PHY_OUI_CICADA 0x03f1
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#define PHY_OUI_VITESSE 0x01c1
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+#define PHY_OUI_REALTEK 0x01c1
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#define PHYID1_OUI_MASK 0x03ff
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#define PHYID1_OUI_SHFT 6
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#define PHYID2_OUI_MASK 0xfc00
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@@ -580,6 +581,13 @@ union ring_type {
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#define PHY_VITESSE_INIT8 0x0100
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#define PHY_VITESSE_INIT9 0x8f82
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#define PHY_VITESSE_INIT10 0x0
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+#define PHY_REALTEK_INIT_REG1 0x1f
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+#define PHY_REALTEK_INIT_REG2 0x19
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+#define PHY_REALTEK_INIT_REG3 0x13
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+#define PHY_REALTEK_INIT1 0x0000
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+#define PHY_REALTEK_INIT2 0x8e00
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+#define PHY_REALTEK_INIT3 0x0001
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+#define PHY_REALTEK_INIT4 0xad17
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#define PHY_GIGABIT 0x0100
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@@ -1114,6 +1122,28 @@ static int phy_init(struct net_device *dev)
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return PHY_ERROR;
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}
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}
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+ if (np->phy_oui == PHY_OUI_REALTEK) {
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ }
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/* set advertise register */
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reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
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@@ -1250,6 +1280,30 @@ static int phy_init(struct net_device *dev)
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return PHY_ERROR;
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}
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}
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+ if (np->phy_oui == PHY_OUI_REALTEK) {
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+ /* reset could have cleared these out, set them back */
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1)) {
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+ printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
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+ return PHY_ERROR;
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+ }
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+ }
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+
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/* some phys clear out pause advertisment on reset, set it back */
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mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
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