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@@ -18,6 +18,11 @@
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#include <mach/mv78xx0.h>
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#include "common.h"
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+#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
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+#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
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+#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
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+#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
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+
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struct pcie_port {
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u8 maj;
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u8 min;
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@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
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start = MV78XX0_PCIE_MEM_PHYS_BASE;
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for (i = 0; i < num_pcie_ports; i++) {
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struct pcie_port *pp = pcie_port + i;
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- char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
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"PCIe %d.%d MEM", pp->maj, pp->min);
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@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
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if (request_resource(&iomem_resource, &pp->res))
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panic("can't allocate PCIe MEM sub-space");
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- snprintf(winname, sizeof(winname), "pcie%d.%d",
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- pp->maj, pp->min);
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-
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- mvebu_mbus_add_window_remap_flags(winname,
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- pp->res.start,
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- resource_size(&pp->res),
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- MVEBU_MBUS_NO_REMAP,
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- MVEBU_MBUS_PCI_MEM);
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- mvebu_mbus_add_window_remap_flags(winname,
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- i * SZ_64K, SZ_64K,
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- 0, MVEBU_MBUS_PCI_IO);
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+ mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
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+ MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
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+ pp->res.start, resource_size(&pp->res));
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+ mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
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+ MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
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+ i * SZ_64K, SZ_64K, 0);
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}
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}
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