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@@ -20,9 +20,12 @@ static inline u32 sdram_selfrefresh_enable(void)
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return saved_lpr;
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}
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-#define sdram_selfrefresh_disable(saved_lpr) at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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-#define wait_for_interrupt_enable() asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
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- : : "r" (0))
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+#define sdram_selfrefresh_disable(saved_lpr) \
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+ at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
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+
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+#define wait_for_interrupt_enable() \
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+ asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
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+ : : "r" (0))
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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#include <mach/at91sam9_ddrsdr.h>
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@@ -59,6 +62,7 @@ static inline u32 sdram_selfrefresh_enable(void)
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at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
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at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
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} while (0)
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+
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#define wait_for_interrupt_enable() cpu_do_idle()
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#else
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@@ -79,11 +83,15 @@ static inline u32 sdram_selfrefresh_enable(void)
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saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
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lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
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- at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
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+ at91_ramc_write(0, AT91_SDRAMC_LPR, lpr |
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+ AT91_SDRAMC_LPCB_SELF_REFRESH);
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return saved_lpr;
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}
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-#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
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-#define wait_for_interrupt_enable() cpu_do_idle()
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+#define sdram_selfrefresh_disable(saved_lpr) \
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+ at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
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+
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+#define wait_for_interrupt_enable() \
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+ cpu_do_idle()
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#endif
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