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@@ -1775,15 +1775,12 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
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dma->device_alloc_chan_resources = ioat2_alloc_chan_resources;
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dma->device_free_chan_resources = ioat2_free_chan_resources;
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- if (is_xeon_cb32(pdev))
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- dma->copy_align = 6;
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-
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dma_cap_set(DMA_INTERRUPT, dma->cap_mask);
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dma->device_prep_dma_interrupt = ioat3_prep_interrupt_lock;
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device->cap = readl(device->reg_base + IOAT_DMA_CAP_OFFSET);
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- if (is_bwd_noraid(pdev))
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+ if (is_xeon_cb32(pdev) || is_bwd_noraid(pdev))
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device->cap &= ~(IOAT_CAP_XOR | IOAT_CAP_PQ | IOAT_CAP_RAID16SS);
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/* dca is incompatible with raid operations */
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@@ -1793,7 +1790,6 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
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if (device->cap & IOAT_CAP_XOR) {
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is_raid_device = true;
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dma->max_xor = 8;
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- dma->xor_align = 6;
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dma_cap_set(DMA_XOR, dma->cap_mask);
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dma->device_prep_dma_xor = ioat3_prep_xor;
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@@ -1812,13 +1808,8 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
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if (device->cap & IOAT_CAP_RAID16SS) {
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dma_set_maxpq(dma, 16, 0);
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- dma->pq_align = 0;
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} else {
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dma_set_maxpq(dma, 8, 0);
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- if (is_xeon_cb32(pdev))
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- dma->pq_align = 6;
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- else
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- dma->pq_align = 0;
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}
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if (!(device->cap & IOAT_CAP_XOR)) {
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@@ -1829,13 +1820,8 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
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if (device->cap & IOAT_CAP_RAID16SS) {
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dma->max_xor = 16;
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- dma->xor_align = 0;
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} else {
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dma->max_xor = 8;
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- if (is_xeon_cb32(pdev))
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- dma->xor_align = 6;
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- else
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- dma->xor_align = 0;
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}
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}
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}
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@@ -1844,14 +1830,6 @@ int ioat3_dma_probe(struct ioatdma_device *device, int dca)
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device->cleanup_fn = ioat3_cleanup_event;
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device->timer_fn = ioat3_timer_event;
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- if (is_xeon_cb32(pdev)) {
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- dma_cap_clear(DMA_XOR_VAL, dma->cap_mask);
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- dma->device_prep_dma_xor_val = NULL;
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-
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- dma_cap_clear(DMA_PQ_VAL, dma->cap_mask);
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- dma->device_prep_dma_pq_val = NULL;
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- }
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-
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/* starting with CB3.3 super extended descriptors are supported */
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if (device->cap & IOAT_CAP_RAID16SS) {
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char pool_name[14];
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