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@@ -33,6 +33,7 @@
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static void __iomem *gic_dist_base;
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static void __iomem *gic_cpu_base;
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+static DEFINE_SPINLOCK(irq_controller_lock);
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/*
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* Routines to acknowledge, disable and enable interrupts
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@@ -52,32 +53,45 @@ static void __iomem *gic_cpu_base;
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static void gic_ack_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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+
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+ spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
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writel(irq, gic_cpu_base + GIC_CPU_EOI);
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+ spin_unlock(&irq_controller_lock);
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}
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static void gic_mask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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+
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+ spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
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+ spin_unlock(&irq_controller_lock);
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}
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static void gic_unmask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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+
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+ spin_lock(&irq_controller_lock);
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writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
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+ spin_unlock(&irq_controller_lock);
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}
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#ifdef CONFIG_SMP
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-static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
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+static void gic_set_cpu(unsigned int irq, cpumask_t mask_val)
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{
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void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
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unsigned int shift = (irq % 4) * 8;
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+ unsigned int cpu = first_cpu(mask_val);
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u32 val;
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+ spin_lock(&irq_controller_lock);
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+ irq_desc[irq].cpu = cpu;
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val = readl(reg) & ~(0xff << shift);
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val |= 1 << (cpu + shift);
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writel(val, reg);
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+ spin_unlock(&irq_controller_lock);
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}
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#endif
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@@ -86,7 +100,7 @@ static struct irqchip gic_chip = {
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.mask = gic_mask_irq,
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.unmask = gic_unmask_irq,
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#ifdef CONFIG_SMP
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- .set_cpu = gic_set_cpu,
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+ .set_affinity = gic_set_cpu,
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#endif
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};
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