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@@ -127,6 +127,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
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case QT2022_PHY_ID:
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phy_type = ixgbe_phy_qt;
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break;
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+ case ATH_PHY_ID:
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+ phy_type = ixgbe_phy_nl;
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+ break;
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default:
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phy_type = ixgbe_phy_unknown;
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break;
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@@ -429,6 +432,261 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
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return 0;
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}
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+/**
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+ * ixgbe_reset_phy_nl - Performs a PHY reset
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+ * @hw: pointer to hardware structure
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+ **/
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+s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
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+{
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+ u16 phy_offset, control, eword, edata, block_crc;
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+ bool end_data = false;
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+ u16 list_offset, data_offset;
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+ u16 phy_data = 0;
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+ s32 ret_val = 0;
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+ u32 i;
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+
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+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
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+ IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
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+
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+ /* reset the PHY and poll for completion */
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+ hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
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+ IXGBE_MDIO_PHY_XS_DEV_TYPE,
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+ (phy_data | IXGBE_MDIO_PHY_XS_RESET));
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+
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+ for (i = 0; i < 100; i++) {
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+ hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
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+ IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
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+ if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
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+ break;
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+ msleep(10);
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+ }
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+
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+ if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
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+ hw_dbg(hw, "PHY reset did not complete.\n");
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+ ret_val = IXGBE_ERR_PHY;
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+ goto out;
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+ }
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+
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+ /* Get init offsets */
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+ ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
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+ &data_offset);
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+ if (ret_val != 0)
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+ goto out;
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+
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+ ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
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+ data_offset++;
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+ while (!end_data) {
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+ /*
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+ * Read control word from PHY init contents offset
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+ */
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+ ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
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+ control = (eword & IXGBE_CONTROL_MASK_NL) >>
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+ IXGBE_CONTROL_SHIFT_NL;
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+ edata = eword & IXGBE_DATA_MASK_NL;
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+ switch (control) {
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+ case IXGBE_DELAY_NL:
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+ data_offset++;
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+ hw_dbg(hw, "DELAY: %d MS\n", edata);
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+ msleep(edata);
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+ break;
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+ case IXGBE_DATA_NL:
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+ hw_dbg(hw, "DATA: \n");
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+ data_offset++;
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+ hw->eeprom.ops.read(hw, data_offset++,
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+ &phy_offset);
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+ for (i = 0; i < edata; i++) {
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+ hw->eeprom.ops.read(hw, data_offset, &eword);
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+ hw->phy.ops.write_reg(hw, phy_offset,
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+ IXGBE_TWINAX_DEV, eword);
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+ hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
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+ phy_offset);
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+ data_offset++;
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+ phy_offset++;
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+ }
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+ break;
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+ case IXGBE_CONTROL_NL:
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+ data_offset++;
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+ hw_dbg(hw, "CONTROL: \n");
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+ if (edata == IXGBE_CONTROL_EOL_NL) {
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+ hw_dbg(hw, "EOL\n");
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+ end_data = true;
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+ } else if (edata == IXGBE_CONTROL_SOL_NL) {
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+ hw_dbg(hw, "SOL\n");
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+ } else {
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+ hw_dbg(hw, "Bad control value\n");
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+ ret_val = IXGBE_ERR_PHY;
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+ goto out;
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+ }
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+ break;
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+ default:
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+ hw_dbg(hw, "Bad control type\n");
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+ ret_val = IXGBE_ERR_PHY;
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+ goto out;
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+ }
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+ }
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+
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+out:
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+ return ret_val;
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+}
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+
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+/**
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+ * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
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+ * the PHY type.
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+ * @hw: pointer to hardware structure
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+ *
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+ * Searches for and indentifies the SFP module. Assings appropriate PHY type.
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+ **/
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+s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
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+{
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+ s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
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+ u32 vendor_oui = 0;
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+ u8 identifier = 0;
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+ u8 comp_codes_1g = 0;
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+ u8 comp_codes_10g = 0;
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+ u8 oui_bytes[4] = {0, 0, 0, 0};
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+ u8 transmission_media = 0;
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+
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+ status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
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+ &identifier);
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+
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+ if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
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+ hw->phy.sfp_type = ixgbe_sfp_type_not_present;
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+ goto out;
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+ }
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+
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+ if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
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+ hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
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+ &comp_codes_1g);
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+ hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
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+ &comp_codes_10g);
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+ hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
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+ &transmission_media);
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+
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+ /* ID Module
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+ * =========
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+ * 0 SFP_DA_CU
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+ * 1 SFP_SR
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+ * 2 SFP_LR
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+ */
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+ if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
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+ hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
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+ else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
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+ hw->phy.sfp_type = ixgbe_sfp_type_sr;
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+ else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
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+ hw->phy.sfp_type = ixgbe_sfp_type_lr;
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+ else
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+ hw->phy.sfp_type = ixgbe_sfp_type_unknown;
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+
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+ /* Determine PHY vendor */
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+ if (hw->phy.type == ixgbe_phy_unknown) {
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+ hw->phy.id = identifier;
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+ hw->phy.ops.read_i2c_eeprom(hw,
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+ IXGBE_SFF_VENDOR_OUI_BYTE0,
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+ &oui_bytes[0]);
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+ hw->phy.ops.read_i2c_eeprom(hw,
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+ IXGBE_SFF_VENDOR_OUI_BYTE1,
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+ &oui_bytes[1]);
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+ hw->phy.ops.read_i2c_eeprom(hw,
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+ IXGBE_SFF_VENDOR_OUI_BYTE2,
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+ &oui_bytes[2]);
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+
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+ vendor_oui =
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+ ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
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+ (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
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+ (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
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+
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+ switch (vendor_oui) {
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+ case IXGBE_SFF_VENDOR_OUI_TYCO:
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+ if (transmission_media &
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+ IXGBE_SFF_TWIN_AX_CAPABLE)
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+ hw->phy.type = ixgbe_phy_tw_tyco;
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+ break;
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+ case IXGBE_SFF_VENDOR_OUI_FTL:
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+ hw->phy.type = ixgbe_phy_sfp_ftl;
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+ break;
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+ case IXGBE_SFF_VENDOR_OUI_AVAGO:
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+ hw->phy.type = ixgbe_phy_sfp_avago;
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+ break;
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+ default:
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+ if (transmission_media &
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+ IXGBE_SFF_TWIN_AX_CAPABLE)
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+ hw->phy.type = ixgbe_phy_tw_unknown;
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+ else
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+ hw->phy.type = ixgbe_phy_sfp_unknown;
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+ break;
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+ }
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+ }
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+ status = 0;
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+ }
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+
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+out:
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+ return status;
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+}
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+
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+/**
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+ * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
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+ * if it supports a given SFP+ module type, if so it returns the offsets to the
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+ * phy init sequence block.
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+ * @hw: pointer to hardware structure
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+ * @list_offset: offset to the SFP ID list
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+ * @data_offset: offset to the SFP data block
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+ **/
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+s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
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+ u16 *list_offset,
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+ u16 *data_offset)
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+{
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+ u16 sfp_id;
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+
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+ if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
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+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
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+
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+ if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
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+ return IXGBE_ERR_SFP_NOT_PRESENT;
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+
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+ if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
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+ (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
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+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
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+
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+ /* Read offset to PHY init contents */
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+ hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
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+
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+ if ((!*list_offset) || (*list_offset == 0xFFFF))
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+ return IXGBE_ERR_PHY;
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+
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+ /* Shift offset to first ID word */
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+ (*list_offset)++;
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+
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+ /*
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+ * Find the matching SFP ID in the EEPROM
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+ * and program the init sequence
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+ */
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+ hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
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+
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+ while (sfp_id != IXGBE_PHY_INIT_END_NL) {
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+ if (sfp_id == hw->phy.sfp_type) {
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+ (*list_offset)++;
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+ hw->eeprom.ops.read(hw, *list_offset, data_offset);
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+ if ((!*data_offset) || (*data_offset == 0xFFFF)) {
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+ hw_dbg(hw, "SFP+ module not supported\n");
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+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
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+ } else {
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+ break;
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+ }
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+ } else {
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+ (*list_offset) += 2;
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+ if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
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+ return IXGBE_ERR_PHY;
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+ }
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+ }
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+
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+ if (sfp_id == IXGBE_PHY_INIT_END_NL) {
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+ hw_dbg(hw, "No matching SFP+ module found\n");
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+ return IXGBE_ERR_SFP_NOT_SUPPORTED;
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+ }
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+
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+ return 0;
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+}
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+
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/**
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* ixgbe_check_phy_link_tnx - Determine link and speed status
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* @hw: pointer to hardware structure
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Donald Skidmore