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@@ -10,12 +10,14 @@
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*/
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#include <linux/kernel.h>
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+#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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+#include <clocksource/samsung_pwm.h>
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#include <linux/sched.h>
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#include <linux/serial_core.h>
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#include <linux/of.h>
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@@ -302,6 +304,13 @@ static struct map_desc exynos5440_iodesc0[] __initdata = {
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},
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};
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+static struct samsung_pwm_variant exynos4_pwm_variant = {
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+ .bits = 32,
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+ .div_base = 0,
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+ .has_tint_cstat = true,
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+ .tclk_mask = 0,
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+};
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+
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void exynos4_restart(char mode, const char *cmd)
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{
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__raw_writel(0x1, S5P_SWRESET);
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@@ -317,9 +326,16 @@ void exynos5_restart(char mode, const char *cmd)
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val = 0x1;
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addr = EXYNOS_SWRESET;
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} else if (of_machine_is_compatible("samsung,exynos5440")) {
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+ u32 status;
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np = of_find_compatible_node(NULL, NULL, "samsung,exynos5440-clock");
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+
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+ addr = of_iomap(np, 0) + 0xbc;
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+ status = __raw_readl(addr);
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+
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addr = of_iomap(np, 0) + 0xcc;
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- val = (0xfff << 20) | (0x1 << 16);
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+ val = __raw_readl(addr);
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+
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+ val = (val & 0xffff0000) | (status & 0xffff);
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} else {
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pr_err("%s: cannot support non-DT\n", __func__);
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return;
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@@ -442,8 +458,20 @@ static void __init exynos5440_map_io(void)
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iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
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}
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+void __init exynos_set_timer_source(u8 channels)
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+{
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+ exynos4_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
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+ exynos4_pwm_variant.output_mask &= ~channels;
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+}
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+
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void __init exynos_init_time(void)
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{
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+ unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
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+ EXYNOS4_IRQ_TIMER0_VIC, EXYNOS4_IRQ_TIMER1_VIC,
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+ EXYNOS4_IRQ_TIMER2_VIC, EXYNOS4_IRQ_TIMER3_VIC,
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+ EXYNOS4_IRQ_TIMER4_VIC,
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+ };
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+
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if (of_have_populated_dt()) {
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#ifdef CONFIG_OF
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of_clk_init(NULL);
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@@ -455,7 +483,14 @@ void __init exynos_init_time(void)
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exynos4_clk_init(NULL, !soc_is_exynos4210(), S5P_VA_CMU, readl(S5P_VA_CHIPID + 8) & 1);
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exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
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#endif
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- mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0, EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
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+#ifdef CONFIG_CLKSRC_SAMSUNG_PWM
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+ if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
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+ samsung_pwm_clocksource_init(S3C_VA_TIMER,
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+ timer_irqs, &exynos4_pwm_variant);
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+ else
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+#endif
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+ mct_init(S5P_VA_SYSTIMER, EXYNOS4_IRQ_MCT_G0,
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+ EXYNOS4_IRQ_MCT_L0, EXYNOS4_IRQ_MCT_L1);
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}
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}
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