|
@@ -13,6 +13,8 @@
|
|
|
|
|
|
#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
|
|
|
#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
|
|
|
+#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
|
|
|
+#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
|
|
|
#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
|
|
|
#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
|
|
|
#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
|
|
@@ -70,6 +72,8 @@
|
|
|
#define MX25_INT_NANDFC 33
|
|
|
#define MX25_INT_LCDC 39
|
|
|
#define MX25_INT_UART5 40
|
|
|
+#define MX25_INT_CAN1 43
|
|
|
+#define MX25_INT_CAN2 44
|
|
|
#define MX25_INT_UART1 45
|
|
|
#define MX25_INT_FEC 57
|
|
|
|