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@@ -172,19 +172,16 @@ qla24xx_pause_risc(struct device_reg_24xx __iomem *reg)
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int rval = QLA_SUCCESS;
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uint32_t cnt;
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- if ((RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0) {
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- WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET |
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- HCCRX_CLR_HOST_INT);
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- RD_REG_DWORD(®->hccr); /* PCI Posting. */
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- WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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- for (cnt = 30000;
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- (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
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- rval == QLA_SUCCESS; cnt--) {
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- if (cnt)
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- udelay(100);
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- else
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- rval = QLA_FUNCTION_TIMEOUT;
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- }
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+ if (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE)
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+ return rval;
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+
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+ WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE);
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+ for (cnt = 30000; (RD_REG_DWORD(®->hccr) & HCCRX_RISC_PAUSE) == 0 &&
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+ rval == QLA_SUCCESS; cnt--) {
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+ if (cnt)
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+ udelay(100);
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+ else
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+ rval = QLA_FUNCTION_TIMEOUT;
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}
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return rval;
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