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@@ -50,7 +50,7 @@
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* Except on Single Channel mode of operation
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* Except on Single Channel mode of operation
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* just slot 0/channel0 filled on this mode
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* just slot 0/channel0 filled on this mode
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* On normal operation mode, the two channels on a branch should be
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* On normal operation mode, the two channels on a branch should be
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- filled together for the same SLOT#
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+ * filled together for the same SLOT#
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* When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
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* When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four
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* channels on both branches should be filled
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* channels on both branches should be filled
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*/
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*/
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@@ -67,16 +67,22 @@
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#define to_csrow(slot, ch, branch) \
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#define to_csrow(slot, ch, branch) \
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(to_channel(ch, branch) | ((slot) << 2))
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(to_channel(ch, branch) | ((slot) << 2))
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-
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-/* Device 16,
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- * Function 0: System Address (not documented)
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- * Function 1: Memory Branch Map, Control, Errors Register
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- * Function 2: FSB Error Registers
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- *
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+/*
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+ * I7300 devices
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* All 3 functions of Device 16 (0,1,2) share the SAME DID and
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* All 3 functions of Device 16 (0,1,2) share the SAME DID and
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* uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
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* uses PCI_DEVICE_ID_INTEL_I7300_MCH_ERR for device 16 (0,1,2),
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* PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
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* PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 and PCI_DEVICE_ID_INTEL_I7300_MCH_FB1
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* for device 21 (0,1).
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* for device 21 (0,1).
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+ */
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+
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+/****************************************************
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+ * i7300 Register definitions for memory enumberation
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+ ****************************************************/
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+
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+/*
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+ * Device 16,
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+ * Function 0: System Address (not documented)
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+ * Function 1: Memory Branch Map, Control, Errors Register
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*/
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*/
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/* OFFSETS for Function 0 */
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/* OFFSETS for Function 0 */
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@@ -94,50 +100,6 @@
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#define MIR1 0x84
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#define MIR1 0x84
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#define MIR2 0x88
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#define MIR2 0x88
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-#if 0
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-#define AMIR0 0x8c
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-#define AMIR1 0x90
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-#define AMIR2 0x94
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-
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-/*TODO: double check it */
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-#define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */
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-
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- /* Fatal error registers */
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-#define FERR_FAT_FBD 0x98
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-
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-/*TODO: double check it */
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-#define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */
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-
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-#define NERR_FAT_FBD 0x9c
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-#define FERR_NF_FBD 0xa0
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-
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- /* Non-fatal error register */
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-#define NERR_NF_FBD 0xa4
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-
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- /* Enable error mask */
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-#define EMASK_FBD 0xa8
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-
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-#define ERR0_FBD 0xac
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-#define ERR1_FBD 0xb0
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-#define ERR2_FBD 0xb4
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-#define MCERR_FBD 0xb8
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-
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-#endif
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-
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-/* TODO: Dev 16 fn1 allows memory error injection - offsets 0x100-0x10b */
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-
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- /* TODO: OFFSETS for Device 16 Function 2 */
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-
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-/*
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- * Device 21,
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- * Function 0: Memory Map Branch 0
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- *
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- * Device 22,
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- * Function 0: Memory Map Branch 1
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- */
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-
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- /* OFFSETS for Function 0 */
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-
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/*
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/*
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* Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
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* Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available
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* memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
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* memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
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@@ -171,37 +133,6 @@ const static u16 mtr_regs [MAX_SLOTS] = {
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#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
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#define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
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#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
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#define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
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-#if 0
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- /* OFFSETS for Function 1 */
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-
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-/* TODO */
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-#define NRECFGLOG 0x74
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-#define RECFGLOG 0x78
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-#define NRECMEMA 0xbe
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-#define NRECMEMB 0xc0
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-#define NRECFB_DIMMA 0xc4
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-#define NRECFB_DIMMB 0xc8
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-#define NRECFB_DIMMC 0xcc
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-#define NRECFB_DIMMD 0xd0
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-#define NRECFB_DIMME 0xd4
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-#define NRECFB_DIMMF 0xd8
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-#define REDMEMA 0xdC
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-#define RECMEMA 0xf0
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-#define RECMEMB 0xf4
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-#define RECFB_DIMMA 0xf8
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-#define RECFB_DIMMB 0xec
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-#define RECFB_DIMMC 0xf0
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-#define RECFB_DIMMD 0xf4
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-#define RECFB_DIMME 0xf8
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-#define RECFB_DIMMF 0xfC
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-
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-/* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */
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-static inline int extract_fbdchan_indx(u32 x)
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-{
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- return (x>>28) & 0x3;
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-}
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-#endif
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-
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#ifdef CONFIG_EDAC_DEBUG
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#ifdef CONFIG_EDAC_DEBUG
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/* MTR NUMROW */
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/* MTR NUMROW */
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static const char *numrow_toString[] = {
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static const char *numrow_toString[] = {
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@@ -220,6 +151,85 @@ static const char *numcol_toString[] = {
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};
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};
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#endif
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#endif
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+/************************************************
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+ * i7300 Register definitions for error detection
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+ ************************************************/
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+/*
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+ * Device 16.2: Global Error Registers
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+ */
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+
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+#define FERR_GLOBAL_LO 0x40
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+static const char *ferr_global_name[] = {
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+ [31] = "Internal MCH Fatal Error",
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+ [30] = "Intel QuickData Technology Device Fatal Error",
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+ [29] = "FSB1 Fatal Error",
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+ [28] = "FSB0 Fatal Error",
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+ [27] = "FBD Channel 3 Fatal Error",
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+ [26] = "FBD Channel 2 Fatal Error",
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+ [25] = "FBD Channel 1 Fatal Error",
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+ [24] = "FBD Channel 0 Fatal Error",
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+ [23] = "PCI Express Device 7Fatal Error",
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+ [22] = "PCI Express Device 6 Fatal Error",
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+ [21] = "PCI Express Device 5 Fatal Error",
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+ [20] = "PCI Express Device 4 Fatal Error",
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+ [19] = "PCI Express Device 3 Fatal Error",
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+ [18] = "PCI Express Device 2 Fatal Error",
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+ [17] = "PCI Express Device 1 Fatal Error",
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+ [16] = "ESI Fatal Error",
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+ [15] = "Internal MCH Non-Fatal Error",
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+ [14] = "Intel QuickData Technology Device Non Fatal Error",
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+ [13] = "FSB1 Non-Fatal Error",
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+ [12] = "FSB 0 Non-Fatal Error",
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+ [11] = "FBD Channel 3 Non-Fatal Error",
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+ [10] = "FBD Channel 2 Non-Fatal Error",
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+ [9] = "FBD Channel 1 Non-Fatal Error",
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+ [8] = "FBD Channel 0 Non-Fatal Error",
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+ [7] = "PCI Express Device 7 Non-Fatal Error",
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+ [6] = "PCI Express Device 6 Non-Fatal Error",
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+ [5] = "PCI Express Device 5 Non-Fatal Error",
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+ [4] = "PCI Express Device 4 Non-Fatal Error",
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+ [3] = "PCI Express Device 3 Non-Fatal Error",
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+ [2] = "PCI Express Device 2 Non-Fatal Error",
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+ [1] = "PCI Express Device 1 Non-Fatal Error",
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+ [0] = "ESI Non-Fatal Error",
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+};
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+
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+#define NERR_GLOBAL 0x44
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+static const char *nerr_global_name[] = {
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+ [31] = "Internal MCH Fatal Error",
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+ [30] = "Intel QuickData Technology Device Fatal Error",
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+ [29] = "FSB1 Fatal Error",
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+ [28] = "FSB0 Fatal Error",
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+ [27] = "FSB2 Fatal Error",
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+ [26] = "FSB3 Fatal Error",
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+ [25] = "Reserved",
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+ [24] = "FBD Channel 0,1,2 or 3 Fatal Error",
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+ [23] = "PCI Express Device 7 Fatal Error",
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+ [22] = "PCI Express Device 6 Fatal Error",
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+ [21] = "PCI Express Device 5 Fatal Error",
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+ [20] = "PCI Express Device 4 Fatal Error",
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+ [19] = "PCI Express Device 3 Fatal Error",
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+ [18] = "PCI Express Device 2 Fatal Error",
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+ [17] = "PCI Express Device 1 Fatal Error",
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+ [16] = "ESI Fatal Error",
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+ [15] = "Internal MCH Non-Fatal Error",
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+ [14] = "Intel QuickData Technology Device Non Fatal Error",
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+ [13] = "FSB1 Non-Fatal Error",
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+ [12] = "FSB0 Non-Fatal Error",
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+ [11] = "FSB2 Non-Fatal Error",
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+ [10] = "FSB3 Non-Fatal Error",
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+ [9] = "Reserved",
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+ [8] = "FBD Channel 0,1, 2 or 3 Non-Fatal Error",
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+ [7] = "PCI Express Device 7 Non-Fatal Error",
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+ [6] = "PCI Express Device 6 Non-Fatal Error",
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+ [5] = "PCI Express Device 5 Non-Fatal Error",
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+ [4] = "PCI Express Device 4 Non-Fatal Error",
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+ [3] = "PCI Express Device 3 Non-Fatal Error",
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+ [2] = "PCI Express Device 2 Non-Fatal Error",
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+ [1] = "PCI Express Device 1 Non-Fatal Error",
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+ [0] = "ESI Non-Fatal Error",
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+};
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+
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#if 0
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#if 0
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/*
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/*
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