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@@ -1219,7 +1219,7 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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@@ -1233,7 +1233,7 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
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if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
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if (reg == RADEON_SRC_PITCH_OFFSET) {
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DRM_ERROR("Cannot src blit from microtiled surface\n");
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return -EINVAL;
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}
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tile_flags |= RADEON_DST_TILE_MICRO;
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@@ -1263,7 +1263,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
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if (c > 16) {
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DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
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pkt->opcode);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return -EINVAL;
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}
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track->num_arrays = c;
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@@ -1272,7 +1272,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for packet3 %d\n",
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pkt->opcode);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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idx_value = radeon_get_ib_value(p, idx);
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@@ -1285,7 +1285,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for packet3 %d\n",
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pkt->opcode);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
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@@ -1298,7 +1298,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for packet3 %d\n",
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pkt->opcode);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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idx_value = radeon_get_ib_value(p, idx);
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@@ -1355,20 +1355,6 @@ int r100_cs_parse_packet0(struct radeon_cs_parser *p,
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return 0;
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}
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-void r100_cs_dump_packet(struct radeon_cs_parser *p,
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- struct radeon_cs_packet *pkt)
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-{
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- volatile uint32_t *ib;
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- unsigned i;
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- unsigned idx;
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-
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- ib = p->ib.ptr;
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- idx = pkt->idx;
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- for (i = 0; i <= (pkt->count + 1); i++, idx++) {
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- DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
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- }
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-}
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-
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/**
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* r100_cs_packet_next_vline() - parse userspace VLINE packet
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* @parser: parser structure holding parsing context.
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@@ -1492,14 +1478,14 @@ int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
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if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
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DRM_ERROR("No packet3 for relocation for packet at %d.\n",
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p3reloc.idx);
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- r100_cs_dump_packet(p, &p3reloc);
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+ radeon_cs_dump_packet(p, &p3reloc);
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return -EINVAL;
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}
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idx = radeon_get_ib_value(p, p3reloc.idx + 1);
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if (idx >= relocs_chunk->length_dw) {
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DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
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idx, relocs_chunk->length_dw);
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- r100_cs_dump_packet(p, &p3reloc);
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+ radeon_cs_dump_packet(p, &p3reloc);
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return -EINVAL;
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}
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/* FIXME: we assume reloc size is 4 dwords */
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@@ -1584,7 +1570,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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break;
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@@ -1601,7 +1587,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->zb.robj = reloc->robj;
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@@ -1614,7 +1600,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->cb[0].robj = reloc->robj;
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@@ -1630,7 +1616,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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@@ -1657,7 +1643,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->textures[0].cube_info[i].offset = idx_value;
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@@ -1675,7 +1661,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->textures[1].cube_info[i].offset = idx_value;
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@@ -1693,7 +1679,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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track->textures[2].cube_info[i].offset = idx_value;
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@@ -1711,7 +1697,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
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@@ -1782,7 +1768,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
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if (r) {
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DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
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idx, reg);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
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@@ -1942,7 +1928,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
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r = r100_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
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@@ -1956,7 +1942,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
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r = r100_cs_packet_next_reloc(p, &reloc);
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if (r) {
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DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
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- r100_cs_dump_packet(p, pkt);
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+ radeon_cs_dump_packet(p, pkt);
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return r;
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}
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ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
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