|
@@ -199,6 +199,12 @@ static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
|
|
|
if (ci->hw_ep_max > ENDPT_MAX)
|
|
|
return -ENODEV;
|
|
|
|
|
|
+ /* Disable all interrupts bits */
|
|
|
+ hw_write(ci, OP_USBINTR, 0xffffffff, 0);
|
|
|
+
|
|
|
+ /* Clear all interrupts status bits*/
|
|
|
+ hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
|
|
|
+
|
|
|
dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
|
|
|
ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
|
|
|
|
|
@@ -434,8 +440,11 @@ static void ci_get_otg_capable(struct ci_hdrc *ci)
|
|
|
ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
|
|
|
DCCPARAMS_DC | DCCPARAMS_HC)
|
|
|
== (DCCPARAMS_DC | DCCPARAMS_HC));
|
|
|
- if (ci->is_otg)
|
|
|
+ if (ci->is_otg) {
|
|
|
dev_dbg(ci->dev, "It is OTG capable controller\n");
|
|
|
+ ci_disable_otg_interrupt(ci, OTGSC_INT_EN_BITS);
|
|
|
+ ci_clear_otg_interrupt(ci, OTGSC_INT_STATUS_BITS);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
static int ci_hdrc_probe(struct platform_device *pdev)
|