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@@ -960,6 +960,7 @@ static inline void dsi_enable_pll_clock(bool enable)
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static void _dsi_print_reset_status(void)
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{
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u32 l;
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+ int b0, b1, b2;
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if (!dss_debug)
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return;
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@@ -977,9 +978,21 @@ static void _dsi_print_reset_status(void)
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l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
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printk("CIO (%d) ", FLD_GET(l, 29, 29));
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+ if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
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+ b0 = 28;
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+ b1 = 27;
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+ b2 = 26;
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+ } else {
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+ b0 = 24;
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+ b1 = 25;
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+ b2 = 26;
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+ }
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+
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l = dsi_read_reg(DSI_DSIPHY_CFG5);
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- printk("PHY (%x, %d, %d, %d)\n",
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- FLD_GET(l, 28, 26),
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+ printk("PHY (%x%x%x, %d, %d, %d)\n",
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+ FLD_GET(l, b0, b0),
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+ FLD_GET(l, b1, b1),
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+ FLD_GET(l, b2, b2),
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FLD_GET(l, 29, 29),
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FLD_GET(l, 30, 30),
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FLD_GET(l, 31, 31));
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