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@@ -39,12 +39,14 @@ static inline void chipco_write32(struct ssb_chipcommon *cc,
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ssb_write32(cc->dev, offset, value);
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ssb_write32(cc->dev, offset, value);
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}
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}
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-static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
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- u32 mask, u32 value)
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+static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
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+ u32 mask, u32 value)
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{
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{
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value &= mask;
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value &= mask;
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value |= chipco_read32(cc, offset) & ~mask;
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value |= chipco_read32(cc, offset) & ~mask;
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chipco_write32(cc, offset, value);
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chipco_write32(cc, offset, value);
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+
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+ return value;
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}
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}
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void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
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void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
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@@ -355,16 +357,37 @@ u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
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{
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{
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return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
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return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
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}
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}
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+EXPORT_SYMBOL(ssb_chipco_gpio_in);
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+
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+u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
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+{
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+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
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+}
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+EXPORT_SYMBOL(ssb_chipco_gpio_out);
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+
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+u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
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+{
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+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
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+}
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+EXPORT_SYMBOL(ssb_chipco_gpio_outen);
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+
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+u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
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+{
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+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
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+}
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+EXPORT_SYMBOL(ssb_chipco_gpio_control);
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-void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
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+u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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{
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- chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
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+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
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}
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}
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+EXPORT_SYMBOL(ssb_chipco_gpio_intmask);
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-void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
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+u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
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{
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{
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- chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
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+ return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
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}
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}
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+EXPORT_SYMBOL(ssb_chipco_gpio_polarity);
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#ifdef CONFIG_SSB_SERIAL
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#ifdef CONFIG_SSB_SERIAL
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int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
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int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
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