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@@ -1,13 +1,14 @@
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* ARM architected timer
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-ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
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-provides per-cpu timers.
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+ARM cores may have a per-core architected timer, which provides per-cpu timers.
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The timer is attached to a GIC to deliver its per-processor interrupts.
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** Timer node properties:
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-- compatible : Should at least contain "arm,armv7-timer".
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+- compatible : Should at least contain one of
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+ "arm,armv7-timer"
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+ "arm,armv8-timer"
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- interrupts : Interrupt list for secure, non-secure, virtual and
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hypervisor timers, in that order.
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