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@@ -29,6 +29,7 @@
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#include <linux/irq.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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+#include <linux/mmc/sdio.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/bitops.h>
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#include <linux/regulator/consumer.h>
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@@ -50,6 +51,9 @@
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#define DW_MCI_RECV_STATUS 2
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#define DW_MCI_DMA_THRESHOLD 16
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+#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
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+#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
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+
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#ifdef CONFIG_MMC_DW_IDMAC
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#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
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SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
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@@ -76,42 +80,39 @@ struct idmac_desc {
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};
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#endif /* CONFIG_MMC_DW_IDMAC */
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-/**
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- * struct dw_mci_slot - MMC slot state
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- * @mmc: The mmc_host representing this slot.
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- * @host: The MMC controller this slot is using.
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- * @quirks: Slot-level quirks (DW_MCI_SLOT_QUIRK_XXX)
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- * @wp_gpio: If gpio_is_valid() we'll use this to read write protect.
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- * @ctype: Card type for this slot.
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- * @mrq: mmc_request currently being processed or waiting to be
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- * processed, or NULL when the slot is idle.
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- * @queue_node: List node for placing this node in the @queue list of
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- * &struct dw_mci.
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- * @clock: Clock rate configured by set_ios(). Protected by host->lock.
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- * @flags: Random state bits associated with the slot.
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- * @id: Number of this slot.
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- * @last_detect_state: Most recently observed card detect state.
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- */
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-struct dw_mci_slot {
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- struct mmc_host *mmc;
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- struct dw_mci *host;
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-
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- int quirks;
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- int wp_gpio;
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-
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- u32 ctype;
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-
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- struct mmc_request *mrq;
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- struct list_head queue_node;
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+static const u8 tuning_blk_pattern_4bit[] = {
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+ 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
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+ 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
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+ 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
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+ 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
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+ 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
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+ 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
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+ 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
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+ 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
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+};
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- unsigned int clock;
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- unsigned long flags;
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-#define DW_MMC_CARD_PRESENT 0
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-#define DW_MMC_CARD_NEED_INIT 1
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- int id;
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- int last_detect_state;
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+static const u8 tuning_blk_pattern_8bit[] = {
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+ 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
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+ 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
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+ 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
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+ 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
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+ 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
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+ 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
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+ 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
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+ 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
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+ 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
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+ 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
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+ 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
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+ 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
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+ 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
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+ 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
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+ 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
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+ 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
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};
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+static inline bool dw_mci_fifo_reset(struct dw_mci *host);
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+static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host);
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+
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#if defined(CONFIG_DEBUG_FS)
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static int dw_mci_req_show(struct seq_file *s, void *v)
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{
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@@ -249,10 +250,15 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
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cmdr = cmd->opcode;
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- if (cmdr == MMC_STOP_TRANSMISSION)
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+ if (cmd->opcode == MMC_STOP_TRANSMISSION ||
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+ cmd->opcode == MMC_GO_IDLE_STATE ||
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+ cmd->opcode == MMC_GO_INACTIVE_STATE ||
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+ (cmd->opcode == SD_IO_RW_DIRECT &&
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+ ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
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cmdr |= SDMMC_CMD_STOP;
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else
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- cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
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+ if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
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+ cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
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if (cmd->flags & MMC_RSP_PRESENT) {
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/* We expect a response, so set this bit */
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@@ -279,6 +285,40 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
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return cmdr;
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}
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+static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
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+{
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+ struct mmc_command *stop;
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+ u32 cmdr;
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+
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+ if (!cmd->data)
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+ return 0;
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+
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+ stop = &host->stop_abort;
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+ cmdr = cmd->opcode;
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+ memset(stop, 0, sizeof(struct mmc_command));
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+
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+ if (cmdr == MMC_READ_SINGLE_BLOCK ||
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+ cmdr == MMC_READ_MULTIPLE_BLOCK ||
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+ cmdr == MMC_WRITE_BLOCK ||
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+ cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
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+ stop->opcode = MMC_STOP_TRANSMISSION;
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+ stop->arg = 0;
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+ stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
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+ } else if (cmdr == SD_IO_RW_EXTENDED) {
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+ stop->opcode = SD_IO_RW_DIRECT;
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+ stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
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+ ((cmd->arg >> 28) & 0x7);
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+ stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
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+ } else {
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+ return 0;
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+ }
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+
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+ cmdr = stop->opcode | SDMMC_CMD_STOP |
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+ SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
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+
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+ return cmdr;
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+}
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+
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static void dw_mci_start_command(struct dw_mci *host,
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struct mmc_command *cmd, u32 cmd_flags)
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{
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@@ -293,9 +333,10 @@ static void dw_mci_start_command(struct dw_mci *host,
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mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
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}
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-static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
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+static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
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{
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- dw_mci_start_command(host, data->stop, host->stop_cmdr);
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+ struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
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+ dw_mci_start_command(host, stop, host->stop_cmdr);
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}
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/* DMA interface functions */
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@@ -304,10 +345,10 @@ static void dw_mci_stop_dma(struct dw_mci *host)
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if (host->using_dma) {
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host->dma_ops->stop(host);
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host->dma_ops->cleanup(host);
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- } else {
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- /* Data transfer was stopped by the interrupt handler */
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- set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
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}
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+
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+ /* Data transfer was stopped by the interrupt handler */
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+ set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
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}
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static int dw_mci_get_dma_dir(struct mmc_data *data)
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@@ -331,6 +372,14 @@ static void dw_mci_dma_cleanup(struct dw_mci *host)
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dw_mci_get_dma_dir(data));
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}
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+static void dw_mci_idmac_reset(struct dw_mci *host)
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+{
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+ u32 bmod = mci_readl(host, BMOD);
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+ /* Software reset of DMA */
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+ bmod |= SDMMC_IDMAC_SWRESET;
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+ mci_writel(host, BMOD, bmod);
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+}
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+
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static void dw_mci_idmac_stop_dma(struct dw_mci *host)
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{
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u32 temp;
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@@ -344,6 +393,7 @@ static void dw_mci_idmac_stop_dma(struct dw_mci *host)
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/* Stop the IDMAC running */
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temp = mci_readl(host, BMOD);
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temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
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+ temp |= SDMMC_IDMAC_SWRESET;
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mci_writel(host, BMOD, temp);
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}
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@@ -435,7 +485,7 @@ static int dw_mci_idmac_init(struct dw_mci *host)
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p->des3 = host->sg_dma;
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p->des0 = IDMAC_DES0_ER;
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- mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
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+ dw_mci_idmac_reset(host);
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/* Mask out interrupts - get Tx & Rx complete only */
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mci_writel(host, IDSTS, IDMAC_INT_CLR);
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@@ -532,6 +582,78 @@ static void dw_mci_post_req(struct mmc_host *mmc,
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data->host_cookie = 0;
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}
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+static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
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+{
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+#ifdef CONFIG_MMC_DW_IDMAC
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+ unsigned int blksz = data->blksz;
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+ const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
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+ u32 fifo_width = 1 << host->data_shift;
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+ u32 blksz_depth = blksz / fifo_width, fifoth_val;
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+ u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
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+ int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
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+
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+ tx_wmark = (host->fifo_depth) / 2;
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+ tx_wmark_invers = host->fifo_depth - tx_wmark;
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+
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+ /*
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+ * MSIZE is '1',
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+ * if blksz is not a multiple of the FIFO width
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+ */
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+ if (blksz % fifo_width) {
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+ msize = 0;
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+ rx_wmark = 1;
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+ goto done;
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+ }
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+
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+ do {
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+ if (!((blksz_depth % mszs[idx]) ||
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+ (tx_wmark_invers % mszs[idx]))) {
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+ msize = idx;
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+ rx_wmark = mszs[idx] - 1;
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+ break;
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+ }
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+ } while (--idx > 0);
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+ /*
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+ * If idx is '0', it won't be tried
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+ * Thus, initial values are uesed
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+ */
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+done:
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+ fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
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+ mci_writel(host, FIFOTH, fifoth_val);
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+#endif
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+}
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+
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+static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
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+{
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+ unsigned int blksz = data->blksz;
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+ u32 blksz_depth, fifo_depth;
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+ u16 thld_size;
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+
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+ WARN_ON(!(data->flags & MMC_DATA_READ));
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+
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+ if (host->timing != MMC_TIMING_MMC_HS200 &&
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+ host->timing != MMC_TIMING_UHS_SDR104)
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+ goto disable;
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+
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+ blksz_depth = blksz / (1 << host->data_shift);
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+ fifo_depth = host->fifo_depth;
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+
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+ if (blksz_depth > fifo_depth)
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+ goto disable;
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+
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+ /*
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+ * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
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+ * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
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+ * Currently just choose blksz.
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+ */
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+ thld_size = blksz;
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+ mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
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+ return;
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+
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+disable:
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+ mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
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+}
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+
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static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
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{
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int sg_len;
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@@ -556,6 +678,14 @@ static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
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(unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
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sg_len);
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+ /*
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+ * Decide the MSIZE and RX/TX Watermark.
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+ * If current block size is same with previous size,
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+ * no need to update fifoth.
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+ */
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+ if (host->prev_blksz != data->blksz)
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+ dw_mci_adjust_fifoth(host, data);
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+
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/* Enable the DMA interface */
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temp = mci_readl(host, CTRL);
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temp |= SDMMC_CTRL_DMA_ENABLE;
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@@ -581,10 +711,12 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
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host->sg = NULL;
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host->data = data;
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- if (data->flags & MMC_DATA_READ)
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+ if (data->flags & MMC_DATA_READ) {
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host->dir_status = DW_MCI_RECV_STATUS;
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- else
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+ dw_mci_ctrl_rd_thld(host, data);
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+ } else {
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host->dir_status = DW_MCI_SEND_STATUS;
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+ }
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if (dw_mci_submit_data_dma(host, data)) {
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int flags = SG_MITER_ATOMIC;
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@@ -606,6 +738,21 @@ static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
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temp = mci_readl(host, CTRL);
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temp &= ~SDMMC_CTRL_DMA_ENABLE;
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mci_writel(host, CTRL, temp);
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+
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+ /*
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+ * Use the initial fifoth_val for PIO mode.
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+ * If next issued data may be transfered by DMA mode,
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+ * prev_blksz should be invalidated.
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+ */
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+ mci_writel(host, FIFOTH, host->fifoth_val);
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+ host->prev_blksz = 0;
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+ } else {
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+ /*
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+ * Keep the current block size.
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+ * It will be used to decide whether to update
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+ * fifoth register next time.
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+ */
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+ host->prev_blksz = data->blksz;
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}
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}
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@@ -632,24 +779,31 @@ static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
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static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
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{
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struct dw_mci *host = slot->host;
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+ unsigned int clock = slot->clock;
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u32 div;
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u32 clk_en_a;
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- if (slot->clock != host->current_speed || force_clkinit) {
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- div = host->bus_hz / slot->clock;
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- if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
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+ if (!clock) {
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+ mci_writel(host, CLKENA, 0);
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+ mci_send_cmd(slot,
|
|
|
+ SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
|
|
|
+ } else if (clock != host->current_speed || force_clkinit) {
|
|
|
+ div = host->bus_hz / clock;
|
|
|
+ if (host->bus_hz % clock && host->bus_hz > clock)
|
|
|
/*
|
|
|
* move the + 1 after the divide to prevent
|
|
|
* over-clocking the card.
|
|
|
*/
|
|
|
div += 1;
|
|
|
|
|
|
- div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
|
|
|
+ div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
|
|
|
|
|
|
- dev_info(&slot->mmc->class_dev,
|
|
|
- "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
|
|
|
- " div = %d)\n", slot->id, host->bus_hz, slot->clock,
|
|
|
- div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
|
|
|
+ if ((clock << div) != slot->__clk_old || force_clkinit)
|
|
|
+ dev_info(&slot->mmc->class_dev,
|
|
|
+ "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
|
|
|
+ slot->id, host->bus_hz, clock,
|
|
|
+ div ? ((host->bus_hz / div) >> 1) :
|
|
|
+ host->bus_hz, div);
|
|
|
|
|
|
/* disable clock */
|
|
|
mci_writel(host, CLKENA, 0);
|
|
@@ -676,9 +830,12 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
|
|
|
mci_send_cmd(slot,
|
|
|
SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
|
|
|
|
|
|
- host->current_speed = slot->clock;
|
|
|
+ /* keep the clock with reflecting clock dividor */
|
|
|
+ slot->__clk_old = clock << div;
|
|
|
}
|
|
|
|
|
|
+ host->current_speed = clock;
|
|
|
+
|
|
|
/* Set the current slot bus width */
|
|
|
mci_writel(host, CTYPE, (slot->ctype << slot->id));
|
|
|
}
|
|
@@ -700,7 +857,9 @@ static void __dw_mci_start_request(struct dw_mci *host,
|
|
|
|
|
|
host->pending_events = 0;
|
|
|
host->completed_events = 0;
|
|
|
+ host->cmd_status = 0;
|
|
|
host->data_status = 0;
|
|
|
+ host->dir_status = 0;
|
|
|
|
|
|
data = cmd->data;
|
|
|
if (data) {
|
|
@@ -724,6 +883,8 @@ static void __dw_mci_start_request(struct dw_mci *host,
|
|
|
|
|
|
if (mrq->stop)
|
|
|
host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
|
|
|
+ else
|
|
|
+ host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
|
|
|
}
|
|
|
|
|
|
static void dw_mci_start_request(struct dw_mci *host,
|
|
@@ -806,14 +967,13 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
regs &= ~((0x1 << slot->id) << 16);
|
|
|
|
|
|
mci_writel(slot->host, UHS_REG, regs);
|
|
|
+ slot->host->timing = ios->timing;
|
|
|
|
|
|
- if (ios->clock) {
|
|
|
- /*
|
|
|
- * Use mirror of ios->clock to prevent race with mmc
|
|
|
- * core ios update when finding the minimum.
|
|
|
- */
|
|
|
- slot->clock = ios->clock;
|
|
|
- }
|
|
|
+ /*
|
|
|
+ * Use mirror of ios->clock to prevent race with mmc
|
|
|
+ * core ios update when finding the minimum.
|
|
|
+ */
|
|
|
+ slot->clock = ios->clock;
|
|
|
|
|
|
if (drv_data && drv_data->set_ios)
|
|
|
drv_data->set_ios(slot->host, ios);
|
|
@@ -939,6 +1099,38 @@ static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
+static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
|
|
|
+{
|
|
|
+ struct dw_mci_slot *slot = mmc_priv(mmc);
|
|
|
+ struct dw_mci *host = slot->host;
|
|
|
+ const struct dw_mci_drv_data *drv_data = host->drv_data;
|
|
|
+ struct dw_mci_tuning_data tuning_data;
|
|
|
+ int err = -ENOSYS;
|
|
|
+
|
|
|
+ if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
|
|
|
+ if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
|
|
|
+ tuning_data.blk_pattern = tuning_blk_pattern_8bit;
|
|
|
+ tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
|
|
|
+ } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
|
|
|
+ tuning_data.blk_pattern = tuning_blk_pattern_4bit;
|
|
|
+ tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
|
|
|
+ } else {
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ } else if (opcode == MMC_SEND_TUNING_BLOCK) {
|
|
|
+ tuning_data.blk_pattern = tuning_blk_pattern_4bit;
|
|
|
+ tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
|
|
|
+ } else {
|
|
|
+ dev_err(host->dev,
|
|
|
+ "Undefined command(%d) for tuning\n", opcode);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (drv_data && drv_data->execute_tuning)
|
|
|
+ err = drv_data->execute_tuning(slot, opcode, &tuning_data);
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
static const struct mmc_host_ops dw_mci_ops = {
|
|
|
.request = dw_mci_request,
|
|
|
.pre_req = dw_mci_pre_req,
|
|
@@ -947,6 +1139,7 @@ static const struct mmc_host_ops dw_mci_ops = {
|
|
|
.get_ro = dw_mci_get_ro,
|
|
|
.get_cd = dw_mci_get_cd,
|
|
|
.enable_sdio_irq = dw_mci_enable_sdio_irq,
|
|
|
+ .execute_tuning = dw_mci_execute_tuning,
|
|
|
};
|
|
|
|
|
|
static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
|
|
@@ -978,7 +1171,7 @@ static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
|
|
|
spin_lock(&host->lock);
|
|
|
}
|
|
|
|
|
|
-static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
|
|
|
+static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
|
|
|
{
|
|
|
u32 status = host->cmd_status;
|
|
|
|
|
@@ -1012,12 +1205,52 @@ static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd
|
|
|
/* newer ip versions need a delay between retries */
|
|
|
if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
|
|
|
mdelay(20);
|
|
|
+ }
|
|
|
|
|
|
- if (cmd->data) {
|
|
|
- dw_mci_stop_dma(host);
|
|
|
- host->data = NULL;
|
|
|
+ return cmd->error;
|
|
|
+}
|
|
|
+
|
|
|
+static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
|
|
|
+{
|
|
|
+ u32 status = host->data_status;
|
|
|
+
|
|
|
+ if (status & DW_MCI_DATA_ERROR_FLAGS) {
|
|
|
+ if (status & SDMMC_INT_DRTO) {
|
|
|
+ data->error = -ETIMEDOUT;
|
|
|
+ } else if (status & SDMMC_INT_DCRC) {
|
|
|
+ data->error = -EILSEQ;
|
|
|
+ } else if (status & SDMMC_INT_EBE) {
|
|
|
+ if (host->dir_status ==
|
|
|
+ DW_MCI_SEND_STATUS) {
|
|
|
+ /*
|
|
|
+ * No data CRC status was returned.
|
|
|
+ * The number of bytes transferred
|
|
|
+ * will be exaggerated in PIO mode.
|
|
|
+ */
|
|
|
+ data->bytes_xfered = 0;
|
|
|
+ data->error = -ETIMEDOUT;
|
|
|
+ } else if (host->dir_status ==
|
|
|
+ DW_MCI_RECV_STATUS) {
|
|
|
+ data->error = -EIO;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ /* SDMMC_INT_SBE is included */
|
|
|
+ data->error = -EIO;
|
|
|
}
|
|
|
+
|
|
|
+ dev_err(host->dev, "data error, status 0x%08x\n", status);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * After an error, there may be data lingering
|
|
|
+ * in the FIFO
|
|
|
+ */
|
|
|
+ dw_mci_fifo_reset(host);
|
|
|
+ } else {
|
|
|
+ data->bytes_xfered = data->blocks * data->blksz;
|
|
|
+ data->error = 0;
|
|
|
}
|
|
|
+
|
|
|
+ return data->error;
|
|
|
}
|
|
|
|
|
|
static void dw_mci_tasklet_func(unsigned long priv)
|
|
@@ -1025,14 +1258,16 @@ static void dw_mci_tasklet_func(unsigned long priv)
|
|
|
struct dw_mci *host = (struct dw_mci *)priv;
|
|
|
struct mmc_data *data;
|
|
|
struct mmc_command *cmd;
|
|
|
+ struct mmc_request *mrq;
|
|
|
enum dw_mci_state state;
|
|
|
enum dw_mci_state prev_state;
|
|
|
- u32 status, ctrl;
|
|
|
+ unsigned int err;
|
|
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
|
state = host->state;
|
|
|
data = host->data;
|
|
|
+ mrq = host->mrq;
|
|
|
|
|
|
do {
|
|
|
prev_state = state;
|
|
@@ -1049,16 +1284,23 @@ static void dw_mci_tasklet_func(unsigned long priv)
|
|
|
cmd = host->cmd;
|
|
|
host->cmd = NULL;
|
|
|
set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
|
|
|
- dw_mci_command_complete(host, cmd);
|
|
|
- if (cmd == host->mrq->sbc && !cmd->error) {
|
|
|
+ err = dw_mci_command_complete(host, cmd);
|
|
|
+ if (cmd == mrq->sbc && !err) {
|
|
|
prev_state = state = STATE_SENDING_CMD;
|
|
|
__dw_mci_start_request(host, host->cur_slot,
|
|
|
- host->mrq->cmd);
|
|
|
+ mrq->cmd);
|
|
|
goto unlock;
|
|
|
}
|
|
|
|
|
|
- if (!host->mrq->data || cmd->error) {
|
|
|
- dw_mci_request_end(host, host->mrq);
|
|
|
+ if (cmd->data && err) {
|
|
|
+ dw_mci_stop_dma(host);
|
|
|
+ send_stop_abort(host, data);
|
|
|
+ state = STATE_SENDING_STOP;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!cmd->data || err) {
|
|
|
+ dw_mci_request_end(host, mrq);
|
|
|
goto unlock;
|
|
|
}
|
|
|
|
|
@@ -1069,8 +1311,7 @@ static void dw_mci_tasklet_func(unsigned long priv)
|
|
|
if (test_and_clear_bit(EVENT_DATA_ERROR,
|
|
|
&host->pending_events)) {
|
|
|
dw_mci_stop_dma(host);
|
|
|
- if (data->stop)
|
|
|
- send_stop_cmd(host, data);
|
|
|
+ send_stop_abort(host, data);
|
|
|
state = STATE_DATA_ERROR;
|
|
|
break;
|
|
|
}
|
|
@@ -1090,60 +1331,27 @@ static void dw_mci_tasklet_func(unsigned long priv)
|
|
|
|
|
|
host->data = NULL;
|
|
|
set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
|
|
|
- status = host->data_status;
|
|
|
-
|
|
|
- if (status & DW_MCI_DATA_ERROR_FLAGS) {
|
|
|
- if (status & SDMMC_INT_DRTO) {
|
|
|
- data->error = -ETIMEDOUT;
|
|
|
- } else if (status & SDMMC_INT_DCRC) {
|
|
|
- data->error = -EILSEQ;
|
|
|
- } else if (status & SDMMC_INT_EBE &&
|
|
|
- host->dir_status ==
|
|
|
- DW_MCI_SEND_STATUS) {
|
|
|
- /*
|
|
|
- * No data CRC status was returned.
|
|
|
- * The number of bytes transferred will
|
|
|
- * be exaggerated in PIO mode.
|
|
|
- */
|
|
|
- data->bytes_xfered = 0;
|
|
|
- data->error = -ETIMEDOUT;
|
|
|
- } else {
|
|
|
- dev_err(host->dev,
|
|
|
- "data FIFO error "
|
|
|
- "(status=%08x)\n",
|
|
|
- status);
|
|
|
- data->error = -EIO;
|
|
|
- }
|
|
|
- /*
|
|
|
- * After an error, there may be data lingering
|
|
|
- * in the FIFO, so reset it - doing so
|
|
|
- * generates a block interrupt, hence setting
|
|
|
- * the scatter-gather pointer to NULL.
|
|
|
- */
|
|
|
- sg_miter_stop(&host->sg_miter);
|
|
|
- host->sg = NULL;
|
|
|
- ctrl = mci_readl(host, CTRL);
|
|
|
- ctrl |= SDMMC_CTRL_FIFO_RESET;
|
|
|
- mci_writel(host, CTRL, ctrl);
|
|
|
- } else {
|
|
|
- data->bytes_xfered = data->blocks * data->blksz;
|
|
|
- data->error = 0;
|
|
|
- }
|
|
|
+ err = dw_mci_data_complete(host, data);
|
|
|
|
|
|
- if (!data->stop) {
|
|
|
- dw_mci_request_end(host, host->mrq);
|
|
|
- goto unlock;
|
|
|
- }
|
|
|
+ if (!err) {
|
|
|
+ if (!data->stop || mrq->sbc) {
|
|
|
+ if (mrq->sbc)
|
|
|
+ data->stop->error = 0;
|
|
|
+ dw_mci_request_end(host, mrq);
|
|
|
+ goto unlock;
|
|
|
+ }
|
|
|
|
|
|
- if (host->mrq->sbc && !data->error) {
|
|
|
- data->stop->error = 0;
|
|
|
- dw_mci_request_end(host, host->mrq);
|
|
|
- goto unlock;
|
|
|
+ /* stop command for open-ended transfer*/
|
|
|
+ if (data->stop)
|
|
|
+ send_stop_abort(host, data);
|
|
|
}
|
|
|
|
|
|
+ /*
|
|
|
+ * If err has non-zero,
|
|
|
+ * stop-abort command has been already issued.
|
|
|
+ */
|
|
|
prev_state = state = STATE_SENDING_STOP;
|
|
|
- if (!data->error)
|
|
|
- send_stop_cmd(host, data);
|
|
|
+
|
|
|
/* fall through */
|
|
|
|
|
|
case STATE_SENDING_STOP:
|
|
@@ -1151,9 +1359,19 @@ static void dw_mci_tasklet_func(unsigned long priv)
|
|
|
&host->pending_events))
|
|
|
break;
|
|
|
|
|
|
+ /* CMD error in data command */
|
|
|
+ if (mrq->cmd->error && mrq->data)
|
|
|
+ dw_mci_fifo_reset(host);
|
|
|
+
|
|
|
host->cmd = NULL;
|
|
|
- dw_mci_command_complete(host, host->mrq->stop);
|
|
|
- dw_mci_request_end(host, host->mrq);
|
|
|
+ host->data = NULL;
|
|
|
+
|
|
|
+ if (mrq->stop)
|
|
|
+ dw_mci_command_complete(host, mrq->stop);
|
|
|
+ else
|
|
|
+ host->cmd_status = 0;
|
|
|
+
|
|
|
+ dw_mci_request_end(host, mrq);
|
|
|
goto unlock;
|
|
|
|
|
|
case STATE_DATA_ERROR:
|
|
@@ -1697,7 +1915,6 @@ static void dw_mci_work_routine_card(struct work_struct *work)
|
|
|
struct mmc_host *mmc = slot->mmc;
|
|
|
struct mmc_request *mrq;
|
|
|
int present;
|
|
|
- u32 ctrl;
|
|
|
|
|
|
present = dw_mci_get_cd(mmc);
|
|
|
while (present != slot->last_detect_state) {
|
|
@@ -1736,11 +1953,10 @@ static void dw_mci_work_routine_card(struct work_struct *work)
|
|
|
case STATE_DATA_ERROR:
|
|
|
if (mrq->data->error == -EINPROGRESS)
|
|
|
mrq->data->error = -ENOMEDIUM;
|
|
|
- if (!mrq->stop)
|
|
|
- break;
|
|
|
/* fall through */
|
|
|
case STATE_SENDING_STOP:
|
|
|
- mrq->stop->error = -ENOMEDIUM;
|
|
|
+ if (mrq->stop)
|
|
|
+ mrq->stop->error = -ENOMEDIUM;
|
|
|
break;
|
|
|
}
|
|
|
|
|
@@ -1763,23 +1979,10 @@ static void dw_mci_work_routine_card(struct work_struct *work)
|
|
|
if (present == 0) {
|
|
|
clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
|
|
|
|
|
|
- /*
|
|
|
- * Clear down the FIFO - doing so generates a
|
|
|
- * block interrupt, hence setting the
|
|
|
- * scatter-gather pointer to NULL.
|
|
|
- */
|
|
|
- sg_miter_stop(&host->sg_miter);
|
|
|
- host->sg = NULL;
|
|
|
-
|
|
|
- ctrl = mci_readl(host, CTRL);
|
|
|
- ctrl |= SDMMC_CTRL_FIFO_RESET;
|
|
|
- mci_writel(host, CTRL, ctrl);
|
|
|
-
|
|
|
+ /* Clear down the FIFO */
|
|
|
+ dw_mci_fifo_reset(host);
|
|
|
#ifdef CONFIG_MMC_DW_IDMAC
|
|
|
- ctrl = mci_readl(host, BMOD);
|
|
|
- /* Software reset of DMA */
|
|
|
- ctrl |= SDMMC_IDMAC_SWRESET;
|
|
|
- mci_writel(host, BMOD, ctrl);
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+ dw_mci_idmac_reset(host);
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#endif
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}
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@@ -1901,6 +2104,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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struct dw_mci_slot *slot;
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const struct dw_mci_drv_data *drv_data = host->drv_data;
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int ctrl_id, ret;
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+ u32 freq[2];
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u8 bus_width;
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mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
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@@ -1916,8 +2120,14 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
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mmc->ops = &dw_mci_ops;
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- mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
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- mmc->f_max = host->bus_hz;
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+ if (of_property_read_u32_array(host->dev->of_node,
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+ "clock-freq-min-max", freq, 2)) {
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+ mmc->f_min = DW_MCI_FREQ_MIN;
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+ mmc->f_max = DW_MCI_FREQ_MAX;
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+ } else {
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+ mmc->f_min = freq[0];
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+ mmc->f_max = freq[1];
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+ }
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if (host->pdata->get_ocr)
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mmc->ocr_avail = host->pdata->get_ocr(id);
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@@ -1964,9 +2174,6 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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mmc->caps |= MMC_CAP_4_BIT_DATA;
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}
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- if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
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- mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
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-
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if (host->pdata->blk_settings) {
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mmc->max_segs = host->pdata->blk_settings->max_segs;
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mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
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@@ -2008,12 +2215,6 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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/* Card initially undetected */
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slot->last_detect_state = 0;
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- /*
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- * Card may have been plugged in prior to boot so we
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- * need to run the detect tasklet
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- */
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- queue_work(host->card_workqueue, &host->card_work);
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-
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return 0;
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err_setup_bus:
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@@ -2074,36 +2275,57 @@ no_dma:
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return;
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}
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-static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
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+static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(500);
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- unsigned int ctrl;
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+ u32 ctrl;
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- mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
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- SDMMC_CTRL_DMA_RESET));
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+ ctrl = mci_readl(host, CTRL);
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+ ctrl |= reset;
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+ mci_writel(host, CTRL, ctrl);
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/* wait till resets clear */
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do {
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ctrl = mci_readl(host, CTRL);
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- if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
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- SDMMC_CTRL_DMA_RESET)))
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+ if (!(ctrl & reset))
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return true;
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} while (time_before(jiffies, timeout));
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- dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
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+ dev_err(host->dev,
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+ "Timeout resetting block (ctrl reset %#x)\n",
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+ ctrl & reset);
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return false;
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}
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+static inline bool dw_mci_fifo_reset(struct dw_mci *host)
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+{
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+ /*
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+ * Reseting generates a block interrupt, hence setting
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+ * the scatter-gather pointer to NULL.
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+ */
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+ if (host->sg) {
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+ sg_miter_stop(&host->sg_miter);
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+ host->sg = NULL;
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+ }
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+
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+ return dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET);
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+}
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+
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+static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
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+{
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+ return dw_mci_ctrl_reset(host,
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+ SDMMC_CTRL_FIFO_RESET |
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+ SDMMC_CTRL_RESET |
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+ SDMMC_CTRL_DMA_RESET);
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+}
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+
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|
#ifdef CONFIG_OF
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static struct dw_mci_of_quirks {
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char *quirk;
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|
int id;
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} of_quirks[] = {
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|
|
{
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|
- .quirk = "supports-highspeed",
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|
- .id = DW_MCI_QUIRK_HIGHSPEED,
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- }, {
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|
.quirk = "broken-cd",
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|
.id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
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|
},
|
|
@@ -2158,6 +2380,15 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
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|
if (of_find_property(np, "enable-sdio-wakeup", NULL))
|
|
|
pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
|
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|
|
+ if (of_find_property(np, "supports-highspeed", NULL))
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|
|
+ pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
|
|
|
+
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|
|
+ if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
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|
|
+ pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
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|
|
+
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|
|
+ if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
|
|
|
+ pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
|
|
|
+
|
|
|
return pdata;
|
|
|
}
|
|
|
|
|
@@ -2221,6 +2452,15 @@ int dw_mci_probe(struct dw_mci *host)
|
|
|
host->bus_hz = clk_get_rate(host->ciu_clk);
|
|
|
}
|
|
|
|
|
|
+ if (drv_data && drv_data->init) {
|
|
|
+ ret = drv_data->init(host);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(host->dev,
|
|
|
+ "implementation specific init failed\n");
|
|
|
+ goto err_clk_ciu;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
if (drv_data && drv_data->setup_clock) {
|
|
|
ret = drv_data->setup_clock(host);
|
|
|
if (ret) {
|
|
@@ -2287,7 +2527,7 @@ int dw_mci_probe(struct dw_mci *host)
|
|
|
}
|
|
|
|
|
|
/* Reset all blocks */
|
|
|
- if (!mci_wait_reset(host->dev, host))
|
|
|
+ if (!dw_mci_ctrl_all_reset(host))
|
|
|
return -ENODEV;
|
|
|
|
|
|
host->dma_ops = host->pdata->dma_ops;
|
|
@@ -2317,8 +2557,8 @@ int dw_mci_probe(struct dw_mci *host)
|
|
|
fifo_size = host->pdata->fifo_depth;
|
|
|
}
|
|
|
host->fifo_depth = fifo_size;
|
|
|
- host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
|
|
|
- ((fifo_size/2) << 0));
|
|
|
+ host->fifoth_val =
|
|
|
+ SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
|
|
|
mci_writel(host, FIFOTH, host->fifoth_val);
|
|
|
|
|
|
/* disable clock to CIU */
|
|
@@ -2456,23 +2696,6 @@ EXPORT_SYMBOL(dw_mci_remove);
|
|
|
*/
|
|
|
int dw_mci_suspend(struct dw_mci *host)
|
|
|
{
|
|
|
- int i, ret = 0;
|
|
|
-
|
|
|
- for (i = 0; i < host->num_slots; i++) {
|
|
|
- struct dw_mci_slot *slot = host->slot[i];
|
|
|
- if (!slot)
|
|
|
- continue;
|
|
|
- ret = mmc_suspend_host(slot->mmc);
|
|
|
- if (ret < 0) {
|
|
|
- while (--i >= 0) {
|
|
|
- slot = host->slot[i];
|
|
|
- if (slot)
|
|
|
- mmc_resume_host(host->slot[i]->mmc);
|
|
|
- }
|
|
|
- return ret;
|
|
|
- }
|
|
|
- }
|
|
|
-
|
|
|
if (host->vmmc)
|
|
|
regulator_disable(host->vmmc);
|
|
|
|
|
@@ -2493,7 +2716,7 @@ int dw_mci_resume(struct dw_mci *host)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- if (!mci_wait_reset(host->dev, host)) {
|
|
|
+ if (!dw_mci_ctrl_all_reset(host)) {
|
|
|
ret = -ENODEV;
|
|
|
return ret;
|
|
|
}
|
|
@@ -2501,8 +2724,15 @@ int dw_mci_resume(struct dw_mci *host)
|
|
|
if (host->use_dma && host->dma_ops->init)
|
|
|
host->dma_ops->init(host);
|
|
|
|
|
|
- /* Restore the old value at FIFOTH register */
|
|
|
+ /*
|
|
|
+ * Restore the initial value at FIFOTH register
|
|
|
+ * And Invalidate the prev_blksz with zero
|
|
|
+ */
|
|
|
mci_writel(host, FIFOTH, host->fifoth_val);
|
|
|
+ host->prev_blksz = 0;
|
|
|
+
|
|
|
+ /* Put in max timeout */
|
|
|
+ mci_writel(host, TMOUT, 0xFFFFFFFF);
|
|
|
|
|
|
mci_writel(host, RINTSTS, 0xFFFFFFFF);
|
|
|
mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
|
|
@@ -2518,10 +2748,6 @@ int dw_mci_resume(struct dw_mci *host)
|
|
|
dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
|
|
|
dw_mci_setup_bus(slot, true);
|
|
|
}
|
|
|
-
|
|
|
- ret = mmc_resume_host(host->slot[i]->mmc);
|
|
|
- if (ret < 0)
|
|
|
- return ret;
|
|
|
}
|
|
|
return 0;
|
|
|
}
|