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@@ -66,7 +66,7 @@
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#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
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#define E1000_CTRL_EXT_EIAME 0x01000000
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#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
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-#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */
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+#define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
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#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */
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#define E1000_CTRL_EXT_LSECCK 0x00001000
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#define E1000_CTRL_EXT_PHYPDEN 0x00100000
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@@ -239,7 +239,7 @@
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#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
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#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */
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#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
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-#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */
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+#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */
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#define HALF_DUPLEX 1
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#define FULL_DUPLEX 2
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@@ -400,7 +400,8 @@
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#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
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#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
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#define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */
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-#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */
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+/* If this bit asserted, the driver should claim the interrupt */
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+#define E1000_ICR_INT_ASSERTED 0x80000000
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#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
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#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
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#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */
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@@ -583,13 +584,13 @@
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#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
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#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES)
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-#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */
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-#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
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-#define E1000_NVM_RW_REG_START 1 /* Start operation */
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-#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
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-#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
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-#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */
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-#define E1000_FLASH_UPDATES 2000
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+#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */
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+#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
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+#define E1000_NVM_RW_REG_START 1 /* Start operation */
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+#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
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+#define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */
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+#define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */
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+#define E1000_FLASH_UPDATES 2000
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/* NVM Word Offsets */
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#define NVM_COMPAT 0x0003
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