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@@ -1092,6 +1092,21 @@ rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
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rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
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rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
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}
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}
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+struct exgmac_reg {
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+ u16 addr;
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+ u16 mask;
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+ u32 val;
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+};
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+
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+static void rtl_write_exgmac_batch(void __iomem *ioaddr,
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+ const struct exgmac_reg *r, int len)
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+{
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+ while (len-- > 0) {
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+ rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
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+ r++;
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+ }
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+}
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+
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static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
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static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
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{
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{
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u8 value = 0xff;
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u8 value = 0xff;
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@@ -3117,6 +3132,18 @@ static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
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RTL_W32(MAC0, low);
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RTL_W32(MAC0, low);
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RTL_R32(MAC0);
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RTL_R32(MAC0);
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+ if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
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+ const struct exgmac_reg e[] = {
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+ { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
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+ { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
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+ { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
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+ { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
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+ low >> 16 },
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+ };
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+
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+ rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
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+ }
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+
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RTL_W8(Cfg9346, Cfg9346_Lock);
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RTL_W8(Cfg9346, Cfg9346_Lock);
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spin_unlock_irq(&tp->lock);
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spin_unlock_irq(&tp->lock);
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