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@@ -1603,6 +1603,10 @@
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* of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
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* of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
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* register. Reset on hard reset. */
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* register. Reset on hard reset. */
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#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
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#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
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+/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
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+ * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
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+ * register. Reset on hard reset. */
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+#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
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/* [RW 32] The following driver registers(1...16) represent 16 drivers and
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/* [RW 32] The following driver registers(1...16) represent 16 drivers and
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32 clients. Each client can be controlled by one driver only. One in each
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32 clients. Each client can be controlled by one driver only. One in each
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bit represent that this driver control the appropriate client (Ex: bit 5
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bit represent that this driver control the appropriate client (Ex: bit 5
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