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@@ -48,14 +48,14 @@ static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
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i++;
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i++;
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} while (((status & 1) == 0) && (i < 50));
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} while (((status & 1) == 0) && (i < 50));
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if (i == 50)
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if (i == 50)
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- CH_ERR("Invalid tpi read from MAC, breaking loop.\n");
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+ pr_err("Invalid tpi read from MAC, breaking loop.\n");
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t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
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t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
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t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);
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t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);
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*val = (vhi << 16) | vlo;
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*val = (vhi << 16) | vlo;
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- /* CH_ERR("rd: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
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+ /* pr_err("rd: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
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((addr&0xe000)>>13), ((addr&0x1e00)>>9),
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((addr&0xe000)>>13), ((addr&0x1e00)>>9),
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((addr&0x01fe)>>1), *val); */
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((addr&0x01fe)>>1), *val); */
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spin_unlock_bh(&adapter->mac_lock);
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spin_unlock_bh(&adapter->mac_lock);
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@@ -66,7 +66,7 @@ static void vsc_write(adapter_t *adapter, u32 addr, u32 data)
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spin_lock_bh(&adapter->mac_lock);
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spin_lock_bh(&adapter->mac_lock);
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t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
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t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
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t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
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t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
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- /* CH_ERR("wr: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
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+ /* pr_err("wr: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
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((addr&0xe000)>>13), ((addr&0x1e00)>>9),
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((addr&0xe000)>>13), ((addr&0x1e00)>>9),
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((addr&0x01fe)>>1), data); */
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((addr&0x01fe)>>1), data); */
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spin_unlock_bh(&adapter->mac_lock);
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spin_unlock_bh(&adapter->mac_lock);
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@@ -225,7 +225,7 @@ static void run_table(adapter_t *adapter, struct init_table *ib, int len)
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for (i = 0; i < len; i++) {
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for (i = 0; i < len; i++) {
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if (ib[i].addr == INITBLOCK_SLEEP) {
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if (ib[i].addr == INITBLOCK_SLEEP) {
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udelay( ib[i].data );
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udelay( ib[i].data );
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- CH_ERR("sleep %d us\n",ib[i].data);
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+ pr_err("sleep %d us\n",ib[i].data);
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} else
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} else
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vsc_write( adapter, ib[i].addr, ib[i].data );
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vsc_write( adapter, ib[i].addr, ib[i].data );
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}
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}
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@@ -241,7 +241,7 @@ static int bist_rd(adapter_t *adapter, int moduleid, int address)
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(address != 0x2) &&
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(address != 0x2) &&
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(address != 0xd) &&
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(address != 0xd) &&
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(address != 0xe))
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(address != 0xe))
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- CH_ERR("No bist address: 0x%x\n", address);
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+ pr_err("No bist address: 0x%x\n", address);
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data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
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data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
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((moduleid & 0xff) << 0));
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((moduleid & 0xff) << 0));
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@@ -251,9 +251,9 @@ static int bist_rd(adapter_t *adapter, int moduleid, int address)
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vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
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vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
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if ((result & (1 << 9)) != 0x0)
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if ((result & (1 << 9)) != 0x0)
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- CH_ERR("Still in bist read: 0x%x\n", result);
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+ pr_err("Still in bist read: 0x%x\n", result);
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else if ((result & (1 << 8)) != 0x0)
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else if ((result & (1 << 8)) != 0x0)
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- CH_ERR("bist read error: 0x%x\n", result);
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+ pr_err("bist read error: 0x%x\n", result);
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return (result & 0xff);
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return (result & 0xff);
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}
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}
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@@ -268,10 +268,10 @@ static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
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(address != 0x2) &&
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(address != 0x2) &&
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(address != 0xd) &&
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(address != 0xd) &&
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(address != 0xe))
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(address != 0xe))
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- CH_ERR("No bist address: 0x%x\n", address);
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+ pr_err("No bist address: 0x%x\n", address);
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if (value > 255)
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if (value > 255)
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- CH_ERR("Suspicious write out of range value: 0x%x\n", value);
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+ pr_err("Suspicious write out of range value: 0x%x\n", value);
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data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
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data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
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((moduleid & 0xff) << 0));
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((moduleid & 0xff) << 0));
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@@ -281,9 +281,9 @@ static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
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vsc_read(adapter, REG_RAM_BIST_CMD, &result);
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vsc_read(adapter, REG_RAM_BIST_CMD, &result);
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if ((result & (1 << 27)) != 0x0)
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if ((result & (1 << 27)) != 0x0)
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- CH_ERR("Still in bist write: 0x%x\n", result);
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+ pr_err("Still in bist write: 0x%x\n", result);
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else if ((result & (1 << 26)) != 0x0)
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else if ((result & (1 << 26)) != 0x0)
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- CH_ERR("bist write error: 0x%x\n", result);
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+ pr_err("bist write error: 0x%x\n", result);
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return 0;
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return 0;
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}
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}
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@@ -306,7 +306,7 @@ static int check_bist(adapter_t *adapter, int moduleid)
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column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +
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column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +
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(bist_rd(adapter,moduleid, 0x0d)));
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(bist_rd(adapter,moduleid, 0x0d)));
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if ((result & 3) != 0x3)
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if ((result & 3) != 0x3)
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- CH_ERR("Result: 0x%x BIST error in ram %d, column: 0x%04x\n",
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+ pr_err("Result: 0x%x BIST error in ram %d, column: 0x%04x\n",
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result, moduleid, column);
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result, moduleid, column);
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return 0;
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return 0;
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}
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}
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