|
@@ -76,7 +76,7 @@
|
|
|
#define IOAT_CHANSTS_OFFSET 0x04 /* 64-bit Channel Status Register */
|
|
|
#define IOAT_CHANSTS_OFFSET_LOW 0x04
|
|
|
#define IOAT_CHANSTS_OFFSET_HIGH 0x08
|
|
|
-#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR 0xFFFFFFFFFFFFFFC0
|
|
|
+#define IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR 0xFFFFFFFFFFFFFFC0UL
|
|
|
#define IOAT_CHANSTS_SOFT_ERR 0x0000000000000010
|
|
|
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS 0x0000000000000007
|
|
|
#define IOAT_CHANSTS_DMA_TRANSFER_STATUS_ACTIVE 0x0
|