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+/*
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+ * Neuros Technologies OSD2 board support
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+ *
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+ * Modified from original 644X-EVM board support.
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+ * 2008 (c) Neuros Technology, LLC.
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+ * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
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+ * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
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+ *
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+ * The Neuros OSD 2.0 is the hardware component of the Neuros Open
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+ * Internet Television Platform. Hardware is very close to TI
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+ * DM644X-EVM board. It has:
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+ * DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
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+ * USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
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+ * Additionaly realtime clock, IR remote control receiver,
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+ * IR Blaster based on MSP430 (firmware although is different
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+ * from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
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+ * with PATA interface, two muxed red-green leds.
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+ *
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+ * For more information please refer to
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+ * http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+#include <linux/platform_device.h>
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+#include <linux/gpio.h>
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+#include <linux/mtd/partitions.h>
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+
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+
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+#include <mach/dm644x.h>
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+#include <mach/i2c.h>
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+#include <mach/serial.h>
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+#include <mach/mux.h>
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+#include <mach/nand.h>
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+#include <mach/mmc.h>
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+#include <mach/usb.h>
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+
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+#define NEUROS_OSD2_PHY_MASK 0x2
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+#define NEUROS_OSD2_MDIO_FREQUENCY 2200000 /* PHY bus frequency */
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+
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+#define DAVINCI_CFC_ATA_BASE 0x01C66000
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+
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+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
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+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
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+
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+#define LXT971_PHY_ID 0x001378e2
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+#define LXT971_PHY_MASK 0xfffffff0
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+
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+#define NTOSD2_AUDIOSOC_I2C_ADDR 0x18
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+#define NTOSD2_MSP430_I2C_ADDR 0x59
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+#define NTOSD2_MSP430_IRQ 2
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+
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+/* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
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+ * 2048 blocks in the device, 64 pages per block, 2048 bytes per
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+ * page.
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+ */
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+
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+#define NAND_BLOCK_SIZE SZ_128K
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+
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+struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
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+ {
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+ /* UBL (a few copies) plus U-Boot */
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+ .name = "bootloader",
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+ .offset = 0,
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+ .size = 15 * NAND_BLOCK_SIZE,
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+ .mask_flags = MTD_WRITEABLE, /* force read-only */
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+ }, {
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+ /* U-Boot environment */
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+ .name = "params",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = 1 * NAND_BLOCK_SIZE,
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+ .mask_flags = 0,
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+ }, {
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+ /* Kernel */
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+ .name = "kernel",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = SZ_4M,
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+ .mask_flags = 0,
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+ }, {
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+ /* File System */
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+ .name = "filesystem",
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+ .offset = MTDPART_OFS_APPEND,
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+ .size = MTDPART_SIZ_FULL,
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+ .mask_flags = 0,
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+ }
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+ /* A few blocks at end hold a flash Bad Block Table. */
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+};
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+
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+static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
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+ .parts = davinci_ntosd2_nandflash_partition,
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+ .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
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+ .ecc_mode = NAND_ECC_HW,
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+ .options = NAND_USE_FLASH_BBT,
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+};
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+
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+static struct resource davinci_ntosd2_nandflash_resource[] = {
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+ {
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+ .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
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+ .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
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+ .flags = IORESOURCE_MEM,
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+ }, {
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+ .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
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+ .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+static struct platform_device davinci_ntosd2_nandflash_device = {
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+ .name = "davinci_nand",
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+ .id = 0,
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+ .dev = {
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+ .platform_data = &davinci_ntosd2_nandflash_data,
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+ },
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+ .num_resources = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
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+ .resource = davinci_ntosd2_nandflash_resource,
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+};
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+
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+static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
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+
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+static struct platform_device davinci_fb_device = {
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+ .name = "davincifb",
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+ .id = -1,
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+ .dev = {
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+ .dma_mask = &davinci_fb_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+ .num_resources = 0,
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+};
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+
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+static struct resource ide_resources[] = {
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+ {
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+ .start = DAVINCI_CFC_ATA_BASE,
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+ .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ {
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+ .start = IRQ_IDE,
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+ .end = IRQ_IDE,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static u64 ide_dma_mask = DMA_BIT_MASK(32);
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+
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+static struct platform_device ide_dev = {
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+ .name = "palm_bk3710",
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+ .id = -1,
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+ .resource = ide_resources,
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+ .num_resources = ARRAY_SIZE(ide_resources),
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+ .dev = {
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+ .dma_mask = &ide_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+};
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+
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+static struct snd_platform_data dm644x_ntosd2_snd_data;
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+
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+static struct gpio_led ntosd2_leds[] = {
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+ { .name = "led1_green", .gpio = GPIO(10), },
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+ { .name = "led1_red", .gpio = GPIO(11), },
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+ { .name = "led2_green", .gpio = GPIO(12), },
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+ { .name = "led2_red", .gpio = GPIO(13), },
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+};
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+
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+static struct gpio_led_platform_data ntosd2_leds_data = {
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+ .num_leds = ARRAY_SIZE(ntosd2_leds),
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+ .leds = ntosd2_leds,
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+};
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+
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+static struct platform_device ntosd2_leds_dev = {
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+ .name = "leds-gpio",
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+ .id = -1,
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+ .dev = {
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+ .platform_data = &ntosd2_leds_data,
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+ },
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+};
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+
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+
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+static struct platform_device *davinci_ntosd2_devices[] __initdata = {
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+ &davinci_fb_device,
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+ &ntosd2_leds_dev,
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+};
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+
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+static struct davinci_uart_config uart_config __initdata = {
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+ .enabled_uarts = (1 << 0),
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+};
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+
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+static void __init davinci_ntosd2_map_io(void)
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+{
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+ dm644x_init();
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+}
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+
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+/*
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+ I2C initialization
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+*/
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+static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
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+ .bus_freq = 20 /* kHz */,
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+ .bus_delay = 100 /* usec */,
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+};
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+
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+static struct i2c_board_info __initdata ntosd2_i2c_info[] = {
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+};
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+
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+static int ntosd2_init_i2c(void)
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+{
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+ int status;
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+
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+ davinci_init_i2c(&ntosd2_i2c_pdata);
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+ status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
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+ if (status == 0) {
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+ status = gpio_direction_input(NTOSD2_MSP430_IRQ);
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+ if (status == 0) {
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+ status = gpio_to_irq(NTOSD2_MSP430_IRQ);
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+ if (status > 0) {
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+ ntosd2_i2c_info[0].irq = status;
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+ i2c_register_board_info(1,
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+ ntosd2_i2c_info,
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+ ARRAY_SIZE(ntosd2_i2c_info));
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+ }
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+ }
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+ }
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+ return status;
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+}
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+
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+static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
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+ .wires = 4,
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+ .version = MMC_CTLR_VERSION_1
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+};
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+
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+
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+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
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+ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
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+#define HAS_ATA 1
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+#else
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+#define HAS_ATA 0
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+#endif
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+
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+#if defined(CONFIG_MTD_NAND_DAVINCI) || \
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+ defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
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+#define HAS_NAND 1
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+#else
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+#define HAS_NAND 0
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+#endif
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+
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+static __init void davinci_ntosd2_init(void)
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+{
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+ struct clk *aemif_clk;
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+ struct davinci_soc_info *soc_info = &davinci_soc_info;
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+ int status;
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+
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+ aemif_clk = clk_get(NULL, "aemif");
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+ clk_enable(aemif_clk);
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+
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+ if (HAS_ATA) {
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+ if (HAS_NAND)
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+ pr_warning("WARNING: both IDE and Flash are "
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+ "enabled, but they share AEMIF pins.\n"
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+ "\tDisable IDE for NAND/NOR support.\n");
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+ davinci_cfg_reg(DM644X_HPIEN_DISABLE);
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+ davinci_cfg_reg(DM644X_ATAEN);
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+ davinci_cfg_reg(DM644X_HDIREN);
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+ platform_device_register(&ide_dev);
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+ } else if (HAS_NAND) {
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+ davinci_cfg_reg(DM644X_HPIEN_DISABLE);
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+ davinci_cfg_reg(DM644X_ATAEN_DISABLE);
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+
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+ /* only one device will be jumpered and detected */
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+ if (HAS_NAND)
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+ platform_device_register(
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+ &davinci_ntosd2_nandflash_device);
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+ }
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+
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+ platform_add_devices(davinci_ntosd2_devices,
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+ ARRAY_SIZE(davinci_ntosd2_devices));
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+
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+ /* Initialize I2C interface specific for this board */
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+ status = ntosd2_init_i2c();
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+ if (status < 0)
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+ pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
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+ " %d\n", status);
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+
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+ davinci_serial_init(&uart_config);
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+ dm644x_init_asp(&dm644x_ntosd2_snd_data);
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+
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+ soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
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+ soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
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+
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+ davinci_setup_usb(1000, 8);
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+ /*
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+ * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
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+ * The AEAWx are five new AEAW pins that can be muxed by separately.
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+ * They are a bitmask for GPIO management. According TI
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+ * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
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+ * gpio(10,11,12,13) for leds any combination of bits works except
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+ * four last. So we are to reset all five.
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+ */
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+ davinci_cfg_reg(DM644X_AEAW0);
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+ davinci_cfg_reg(DM644X_AEAW1);
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+ davinci_cfg_reg(DM644X_AEAW2);
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+ davinci_cfg_reg(DM644X_AEAW3);
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+ davinci_cfg_reg(DM644X_AEAW4);
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+
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+ davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
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+}
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+
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+static __init void davinci_ntosd2_irq_init(void)
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+{
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+ davinci_irq_init();
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+}
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+
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+MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
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+ /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
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+ .phys_io = IO_PHYS,
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+ .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
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+ .boot_params = (DAVINCI_DDR_BASE + 0x100),
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+ .map_io = davinci_ntosd2_map_io,
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+ .init_irq = davinci_ntosd2_irq_init,
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+ .timer = &davinci_timer,
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+ .init_machine = davinci_ntosd2_init,
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+MACHINE_END
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Andrey Porodko