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@@ -20,6 +20,7 @@
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*/
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*/
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#define TARGET_DDR 0
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#define TARGET_DDR 0
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#define TARGET_DEV_BUS 1
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#define TARGET_DEV_BUS 1
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+#define TARGET_SRAM 3
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#define TARGET_PCIE 4
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#define TARGET_PCIE 4
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#define ATTR_DEV_SPI_ROM 0x1e
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#define ATTR_DEV_SPI_ROM 0x1e
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#define ATTR_DEV_BOOT 0x1d
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#define ATTR_DEV_BOOT 0x1d
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@@ -30,6 +31,7 @@
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_DEV_CS0 0x3e
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#define ATTR_PCIE_IO 0xe0
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#define ATTR_PCIE_IO 0xe0
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#define ATTR_PCIE_MEM 0xe8
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#define ATTR_PCIE_MEM 0xe8
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+#define ATTR_SRAM 0x01
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/*
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/*
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* Helpers to get DDR bank info
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* Helpers to get DDR bank info
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@@ -48,7 +50,6 @@
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struct mbus_dram_target_info kirkwood_mbus_dram_info;
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struct mbus_dram_target_info kirkwood_mbus_dram_info;
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-static int __initdata win_alloc_count;
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static int __init cpu_win_can_remap(int win)
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static int __init cpu_win_can_remap(int win)
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{
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{
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@@ -112,7 +113,11 @@ void __init kirkwood_setup_cpu_mbus(void)
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setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
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setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
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TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
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TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
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- win_alloc_count = 3;
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+ /*
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+ * Setup window for SRAM.
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+ */
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+ setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
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+ TARGET_SRAM, ATTR_SRAM, -1);
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/*
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/*
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* Setup MBUS dram target info.
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* Setup MBUS dram target info.
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@@ -140,8 +145,3 @@ void __init kirkwood_setup_cpu_mbus(void)
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}
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}
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kirkwood_mbus_dram_info.num_cs = cs;
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kirkwood_mbus_dram_info.num_cs = cs;
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}
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}
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-
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-void __init kirkwood_setup_sram_win(u32 base, u32 size)
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-{
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- setup_cpu_win(win_alloc_count++, base, size, 0x03, 0x00, -1);
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-}
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