|
@@ -1174,23 +1174,16 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
|
|
|
|
|
|
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
|
|
|
{
|
|
|
- u16 ctl, v;
|
|
|
- int err;
|
|
|
-
|
|
|
- err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
|
|
|
- if (err)
|
|
|
- return;
|
|
|
-
|
|
|
- v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
|
|
|
+ int readrq;
|
|
|
+ u16 v;
|
|
|
|
|
|
+ readrq = pcie_get_readrq(rdev->pdev);
|
|
|
+ v = ffs(readrq) - 8;
|
|
|
/* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
|
|
|
* to avoid hangs or perfomance issues
|
|
|
*/
|
|
|
- if ((v == 0) || (v == 6) || (v == 7)) {
|
|
|
- ctl &= ~PCI_EXP_DEVCTL_READRQ;
|
|
|
- ctl |= (2 << 12);
|
|
|
- pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
|
|
|
- }
|
|
|
+ if ((v == 0) || (v == 6) || (v == 7))
|
|
|
+ pcie_set_readrq(rdev->pdev, 512);
|
|
|
}
|
|
|
|
|
|
static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
|