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@@ -252,6 +252,9 @@
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#define CLK_RESET_CCLK_RUN_POLICY 2
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#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
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+/* PLLM override registers */
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+#define PMC_PLLM_WB0_OVERRIDE 0x1dc
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+
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#ifdef CONFIG_PM_SLEEP
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static struct cpu_clk_suspend_context {
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u32 pllx_misc;
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@@ -563,6 +566,18 @@ static struct tegra_clk_pll_params pll_c_params = {
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.lock_delay = 300,
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};
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+static struct div_nmp pllm_nmp = {
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+ .divn_shift = 8,
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+ .divn_width = 10,
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+ .override_divn_shift = 5,
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+ .divm_shift = 0,
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+ .divm_width = 5,
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+ .override_divm_shift = 0,
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+ .divp_shift = 20,
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+ .divp_width = 3,
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+ .override_divp_shift = 15,
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+};
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+
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static struct tegra_clk_pll_params pll_m_params = {
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.input_min = 2000000,
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.input_max = 31000000,
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@@ -575,6 +590,9 @@ static struct tegra_clk_pll_params pll_m_params = {
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.lock_mask = PLL_BASE_LOCK,
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.lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
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.lock_delay = 300,
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+ .div_nmp = &pllm_nmp,
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+ .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
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+ .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
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};
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static struct tegra_clk_pll_params pll_p_params = {
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