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@@ -48,9 +48,9 @@
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* replacing the low 96 bits with zero does not affect functionality.
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* - If the host writes to the last dword address of such a register
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* (i.e. the high 32 bits) the underlying register will always be
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- * written. If the collector does not hold values for the low 96
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- * bits of the register, they will be written as zero. Writing to
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- * the last qword does not have this effect and must not be done.
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+ * written. If the collector and the current write together do not
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+ * provide values for all 128 bits of the register, the low 96 bits
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+ * will be written as zero.
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* - If the host writes to the address of any other part of such a
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* register while the collector already holds values for some other
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* register, the write is discarded and the collector maintains its
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@@ -103,6 +103,7 @@ static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
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_efx_writed(efx, value->u32[2], reg + 8);
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_efx_writed(efx, value->u32[3], reg + 12);
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#endif
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+ wmb();
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mmiowb();
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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@@ -125,6 +126,7 @@ static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
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__raw_writel((__force u32)value->u32[0], membase + addr);
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__raw_writel((__force u32)value->u32[1], membase + addr + 4);
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#endif
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+ wmb();
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mmiowb();
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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}
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@@ -139,6 +141,7 @@ static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
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/* No lock required */
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_efx_writed(efx, value->u32[0], reg);
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+ wmb();
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}
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/* Read a 128-bit CSR, locking as appropriate. */
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@@ -237,12 +240,14 @@ static inline void _efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
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#ifdef EFX_USE_QWORD_IO
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_efx_writeq(efx, value->u64[0], reg + 0);
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+ _efx_writeq(efx, value->u64[1], reg + 8);
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#else
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_efx_writed(efx, value->u32[0], reg + 0);
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_efx_writed(efx, value->u32[1], reg + 4);
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-#endif
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_efx_writed(efx, value->u32[2], reg + 8);
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_efx_writed(efx, value->u32[3], reg + 12);
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+#endif
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+ wmb();
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}
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#define efx_writeo_page(efx, value, reg, page) \
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_efx_writeo_page(efx, value, \
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