|
@@ -305,12 +305,6 @@ static int snd_atiixp_update_bits(atiixp_t *chip, unsigned int reg,
|
|
#define atiixp_update(chip,reg,mask,val) \
|
|
#define atiixp_update(chip,reg,mask,val) \
|
|
snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
|
|
snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
|
|
|
|
|
|
-/* delay for one tick */
|
|
|
|
-#define do_delay() do { \
|
|
|
|
- schedule_timeout_uninterruptible(1); \
|
|
|
|
-} while (0)
|
|
|
|
-
|
|
|
|
-
|
|
|
|
/*
|
|
/*
|
|
* handling DMA packets
|
|
* handling DMA packets
|
|
*
|
|
*
|
|
@@ -495,7 +489,7 @@ static int snd_atiixp_aclink_reset(atiixp_t *chip)
|
|
atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
|
|
atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
|
|
ATI_REG_CMD_AC_SYNC);
|
|
ATI_REG_CMD_AC_SYNC);
|
|
atiixp_read(chip, CMD);
|
|
atiixp_read(chip, CMD);
|
|
- do_delay();
|
|
|
|
|
|
+ msleep(1);
|
|
atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
|
|
atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
|
|
if (--timeout) {
|
|
if (--timeout) {
|
|
snd_printk(KERN_ERR "atiixp-modem: codec reset timeout\n");
|
|
snd_printk(KERN_ERR "atiixp-modem: codec reset timeout\n");
|
|
@@ -543,9 +537,9 @@ static int snd_atiixp_codec_detect(atiixp_t *chip)
|
|
chip->codec_not_ready_bits = 0;
|
|
chip->codec_not_ready_bits = 0;
|
|
atiixp_write(chip, IER, CODEC_CHECK_BITS);
|
|
atiixp_write(chip, IER, CODEC_CHECK_BITS);
|
|
/* wait for the interrupts */
|
|
/* wait for the interrupts */
|
|
- timeout = HZ / 10;
|
|
|
|
|
|
+ timeout = 50;
|
|
while (timeout-- > 0) {
|
|
while (timeout-- > 0) {
|
|
- do_delay();
|
|
|
|
|
|
+ msleep(1);
|
|
if (chip->codec_not_ready_bits)
|
|
if (chip->codec_not_ready_bits)
|
|
break;
|
|
break;
|
|
}
|
|
}
|