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@@ -264,17 +264,17 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
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SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
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static struct clk div4_clks[DIV4_NR] = {
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- [DIV4_I] = DIV4(FRQCRA, 20, 0xfff, CLK_ENABLE_ON_INIT),
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- [DIV4_ZG] = DIV4(FRQCRA, 16, 0xbff, CLK_ENABLE_ON_INIT),
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- [DIV4_M3] = DIV4(FRQCRA, 12, 0xfff, CLK_ENABLE_ON_INIT),
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- [DIV4_B] = DIV4(FRQCRA, 8, 0xfff, CLK_ENABLE_ON_INIT),
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- [DIV4_M1] = DIV4(FRQCRA, 4, 0xfff, 0),
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- [DIV4_M2] = DIV4(FRQCRA, 0, 0xfff, 0),
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- [DIV4_Z] = DIV4(FRQCRB, 24, 0xbff, 0),
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- [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xfff, 0),
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- [DIV4_ZT] = DIV4(FRQCRB, 16, 0xfff, 0),
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- [DIV4_ZX] = DIV4(FRQCRB, 12, 0xfff, 0),
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- [DIV4_HP] = DIV4(FRQCRB, 4, 0xfff, 0),
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+ [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
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+ [DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
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+ [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
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+ [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
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+ [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
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+ [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
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+ [DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
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+ [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
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+ [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
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+ [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
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+ [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
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};
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enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
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