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-/*
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- * Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
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- *
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- * ADDI-DATA GmbH
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- * Dieselstrasse 3
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- * D-77833 Ottersweier
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- * Tel: +19(0)7223/9493-0
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- * Fax: +49(0)7223/9493-92
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- * http://www.addi-data.com
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- * info@addi-data.com
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License as published by the Free
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- * Software Foundation; either version 2 of the License, or (at your option)
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- * any later version.
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- */
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-
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-/* Header file for AMCC s 5933 */
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-
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-#ifndef _AMCC_S5933_H_
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-#define _AMCC_S5933_H_
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-
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-#include "../../comedidev.h"
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-
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-/* written on base0 */
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-#define FIFO_ADVANCE_ON_BYTE_2 0x20000000
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-
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-/* added for step 6 dma written on base2 */
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-#define AMWEN_ENABLE 0x02
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-
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-#define A2P_FIFO_WRITE_ENABLE 0x01
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-
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-/* for transfer count enable bit */
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-#define AGCSTS_TC_ENABLE 0x10000000
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-
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-/*
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- * ADDON RELATED ADDITIONS
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- */
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-/* Constant */
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-#define APCI3120_ENABLE_TRANSFER_ADD_ON_LOW 0x00
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-#define APCI3120_ENABLE_TRANSFER_ADD_ON_HIGH 0x1200
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-#define APCI3120_A2P_FIFO_MANAGEMENT 0x04000400L
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-#define APCI3120_AMWEN_ENABLE 0x02
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-#define APCI3120_A2P_FIFO_WRITE_ENABLE 0x01
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-#define APCI3120_FIFO_ADVANCE_ON_BYTE_2 0x20000000L
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-#define APCI3120_ENABLE_WRITE_TC_INT 0x00004000L
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-#define APCI3120_CLEAR_WRITE_TC_INT 0x00040000L
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-#define APCI3120_DISABLE_AMWEN_AND_A2P_FIFO_WRITE 0x0
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-#define APCI3120_DISABLE_BUS_MASTER_ADD_ON 0x0
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-#define APCI3120_DISABLE_BUS_MASTER_PCI 0x0
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-
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-/* ADD_ON ::: this needed since apci supports 16 bit interface to add on */
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-#define APCI3120_ADD_ON_AGCSTS_LOW 0x3C
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-#define APCI3120_ADD_ON_AGCSTS_HIGH (APCI3120_ADD_ON_AGCSTS_LOW + 2)
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-#define APCI3120_ADD_ON_MWAR_LOW 0x24
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-#define APCI3120_ADD_ON_MWAR_HIGH (APCI3120_ADD_ON_MWAR_LOW + 2)
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-#define APCI3120_ADD_ON_MWTC_LOW 0x058
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-#define APCI3120_ADD_ON_MWTC_HIGH (APCI3120_ADD_ON_MWTC_LOW + 2)
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-
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-/* AMCC */
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-#define APCI3120_AMCC_OP_MCSR 0x3C
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-#define APCI3120_AMCC_OP_REG_INTCSR 0x38
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-
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-/*
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- * AMCC Operation Register Offsets - PCI
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- */
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-#define AMCC_OP_REG_OMB1 0x00
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-#define AMCC_OP_REG_OMB2 0x04
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-#define AMCC_OP_REG_OMB3 0x08
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-#define AMCC_OP_REG_OMB4 0x0c
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-#define AMCC_OP_REG_IMB1 0x10
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-#define AMCC_OP_REG_IMB2 0x14
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-#define AMCC_OP_REG_IMB3 0x18
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-#define AMCC_OP_REG_IMB4 0x1c
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-#define AMCC_OP_REG_FIFO 0x20
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-#define AMCC_OP_REG_MWAR 0x24
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-#define AMCC_OP_REG_MWTC 0x28
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-#define AMCC_OP_REG_MRAR 0x2c
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-#define AMCC_OP_REG_MRTC 0x30
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-#define AMCC_OP_REG_MBEF 0x34
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-#define AMCC_OP_REG_INTCSR 0x38
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-/* int source */
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-#define AMCC_OP_REG_INTCSR_SRC (AMCC_OP_REG_INTCSR + 2)
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-/* FIFO ctrl */
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-#define AMCC_OP_REG_INTCSR_FEC (AMCC_OP_REG_INTCSR + 3)
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-#define AMCC_OP_REG_MCSR 0x3c
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-/* Data in byte 2 */
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-#define AMCC_OP_REG_MCSR_NVDATA (AMCC_OP_REG_MCSR + 2)
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-/* Command in byte 3 */
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-#define AMCC_OP_REG_MCSR_NVCMD (AMCC_OP_REG_MCSR + 3)
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-
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-#define AMCC_FIFO_DEPTH_DWORD 8
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-#define AMCC_FIFO_DEPTH_BYTES (8 * sizeof(u32))
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-
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-/*
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- * AMCC Operation Registers Size - PCI
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- */
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-#define AMCC_OP_REG_SIZE 64 /* in bytes */
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-
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-/*
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- * AMCC Operation Register Offsets - Add-on
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- */
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-#define AMCC_OP_REG_AIMB1 0x00
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-#define AMCC_OP_REG_AIMB2 0x04
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-#define AMCC_OP_REG_AIMB3 0x08
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-#define AMCC_OP_REG_AIMB4 0x0c
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-#define AMCC_OP_REG_AOMB1 0x10
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-#define AMCC_OP_REG_AOMB2 0x14
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-#define AMCC_OP_REG_AOMB3 0x18
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-#define AMCC_OP_REG_AOMB4 0x1c
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-#define AMCC_OP_REG_AFIFO 0x20
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-#define AMCC_OP_REG_AMWAR 0x24
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-#define AMCC_OP_REG_APTA 0x28
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-#define AMCC_OP_REG_APTD 0x2c
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-#define AMCC_OP_REG_AMRAR 0x30
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-#define AMCC_OP_REG_AMBEF 0x34
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-#define AMCC_OP_REG_AINT 0x38
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-#define AMCC_OP_REG_AGCSTS 0x3c
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-#define AMCC_OP_REG_AMWTC 0x58
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-#define AMCC_OP_REG_AMRTC 0x5c
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-
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-/*
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- * AMCC - Add-on General Control/Status Register
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- */
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-#define AGCSTS_CONTROL_MASK 0xfffff000
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-#define AGCSTS_NV_ACC_MASK 0xe0000000
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-#define AGCSTS_RESET_MASK 0x0e000000
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-#define AGCSTS_NV_DA_MASK 0x00ff0000
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-#define AGCSTS_BIST_MASK 0x0000f000
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-#define AGCSTS_STATUS_MASK 0x000000ff
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-#define AGCSTS_TCZERO_MASK 0x000000c0
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-#define AGCSTS_FIFO_ST_MASK 0x0000003f
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-
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-#define AGCSTS_RESET_MBFLAGS 0x08000000
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-#define AGCSTS_RESET_P2A_FIFO 0x04000000
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-#define AGCSTS_RESET_A2P_FIFO 0x02000000
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-#define AGCSTS_RESET_FIFOS (AGCSTS_RESET_A2P_FIFO | AGCSTS_RESET_P2A_FIFO)
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-
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-#define AGCSTS_A2P_TCOUNT 0x00000080
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-#define AGCSTS_P2A_TCOUNT 0x00000040
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-
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-#define AGCSTS_FS_P2A_EMPTY 0x00000020
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-#define AGCSTS_FS_P2A_HALF 0x00000010
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-#define AGCSTS_FS_P2A_FULL 0x00000008
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-
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-#define AGCSTS_FS_A2P_EMPTY 0x00000004
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-#define AGCSTS_FS_A2P_HALF 0x00000002
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-#define AGCSTS_FS_A2P_FULL 0x00000001
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-
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-/*
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- * AMCC - Add-on Interrupt Control/Status Register
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- */
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-#define AINT_INT_MASK 0x00ff0000
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-#define AINT_SEL_MASK 0x0000ffff
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-#define AINT_IS_ENSEL_MASK 0x00001f1f
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-
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-#define AINT_INT_ASSERTED 0x00800000
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-#define AINT_BM_ERROR 0x00200000
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-#define AINT_BIST_INT 0x00100000
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-
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-#define AINT_RT_COMPLETE 0x00080000
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-#define AINT_WT_COMPLETE 0x00040000
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-
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-#define AINT_OUT_MB_INT 0x00020000
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-#define AINT_IN_MB_INT 0x00010000
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-
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-#define AINT_READ_COMPL 0x00008000
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-#define AINT_WRITE_COMPL 0x00004000
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-
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-#define AINT_OMB_ENABLE 0x00001000
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-#define AINT_OMB_SELECT 0x00000c00
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-#define AINT_OMB_BYTE 0x00000300
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-
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-#define AINT_IMB_ENABLE 0x00000010
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-#define AINT_IMB_SELECT 0x0000000c
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-#define AINT_IMB_BYTE 0x00000003
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-
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-/* Enable Bus Mastering */
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-#define EN_A2P_TRANSFERS 0x00000400
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-/* FIFO Flag Reset */
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-#define RESET_A2P_FLAGS 0x04000000L
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-/* FIFO Relative Priority */
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-#define A2P_HI_PRIORITY 0x00000100L
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-/* Identify Interrupt Sources */
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-#define ANY_S593X_INT 0x00800000L
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-#define READ_TC_INT 0x00080000L
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-#define WRITE_TC_INT 0x00040000L
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-#define IN_MB_INT 0x00020000L
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-#define MASTER_ABORT_INT 0x00100000L
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-#define TARGET_ABORT_INT 0x00200000L
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-#define BUS_MASTER_INT 0x00200000L
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-
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-#endif
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