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@@ -73,6 +73,7 @@ enum {
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RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
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board_ahci = 0,
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+ board_ahci_vt8251 = 1,
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/* global controller registers */
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HOST_CAP = 0x00, /* host capabilities */
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@@ -153,6 +154,9 @@ enum {
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/* hpriv->flags bits */
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AHCI_FLAG_MSI = (1 << 0),
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+
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+ /* ap->flags bits */
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+ AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
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};
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struct ahci_cmd_hdr {
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@@ -255,6 +259,16 @@ static const struct ata_port_info ahci_port_info[] = {
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.udma_mask = 0x7f, /* udma0-6 ; FIXME */
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.port_ops = &ahci_ops,
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},
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+ /* board_ahci_vt8251 */
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+ {
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+ .sht = &ahci_sht,
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+ .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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+ ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
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+ AHCI_FLAG_RESET_NEEDS_CLO,
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+ .pio_mask = 0x1f, /* pio0-4 */
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+ .udma_mask = 0x7f, /* udma0-6 ; FIXME */
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+ .port_ops = &ahci_ops,
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+ },
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};
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static const struct pci_device_id ahci_pci_tbl[] = {
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@@ -296,6 +310,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
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board_ahci }, /* ATI SB600 non-raid */
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{ PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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board_ahci }, /* ATI SB600 raid */
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+ { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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+ board_ahci_vt8251 }, /* VIA VT8251 */
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{ } /* terminate list */
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};
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@@ -516,9 +532,29 @@ static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
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pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
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}
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-static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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+static int ahci_clo(struct ata_port *ap)
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{
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+ void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
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struct ahci_host_priv *hpriv = ap->host_set->private_data;
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+ u32 tmp;
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+
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+ if (!(hpriv->cap & HOST_CAP_CLO))
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+ return -EOPNOTSUPP;
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+
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+ tmp = readl(port_mmio + PORT_CMD);
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+ tmp |= PORT_CMD_CLO;
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+ writel(tmp, port_mmio + PORT_CMD);
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+
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+ tmp = ata_wait_register(port_mmio + PORT_CMD,
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+ PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
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+ if (tmp & PORT_CMD_CLO)
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+ return -EIO;
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+
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+ return 0;
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+}
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+
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+static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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+{
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struct ahci_port_priv *pp = ap->private_data;
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void __iomem *mmio = ap->host_set->mmio_base;
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void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
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@@ -547,21 +583,13 @@ static int ahci_softreset(struct ata_port *ap, unsigned int *class)
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/* check BUSY/DRQ, perform Command List Override if necessary */
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ahci_tf_read(ap, &tf);
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if (tf.command & (ATA_BUSY | ATA_DRQ)) {
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- if (!(hpriv->cap & HOST_CAP_CLO)) {
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- rc = -EIO;
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- reason = "port busy but no CLO";
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- goto fail_restart;
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- }
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-
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- tmp = readl(port_mmio + PORT_CMD);
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- tmp |= PORT_CMD_CLO;
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- writel(tmp, port_mmio + PORT_CMD);
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+ rc = ahci_clo(ap);
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- tmp = ata_wait_register(port_mmio + PORT_CMD,
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- PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
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- if (tmp & PORT_CMD_CLO) {
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- rc = -EIO;
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- reason = "CLO failed";
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+ if (rc == -EOPNOTSUPP) {
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+ reason = "port busy but CLO unavailable";
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+ goto fail_restart;
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+ } else if (rc) {
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+ reason = "port busy but CLO failed";
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goto fail_restart;
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}
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}
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@@ -672,6 +700,12 @@ static void ahci_postreset(struct ata_port *ap, unsigned int *class)
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static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
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{
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+ if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
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+ (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
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+ /* ATA_BUSY hasn't cleared, so send a CLO */
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+ ahci_clo(ap);
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+ }
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+
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return ata_drive_probe_reset(ap, ata_std_probeinit,
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ahci_softreset, ahci_hardreset,
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ahci_postreset, classes);
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