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@@ -13,7 +13,7 @@ all pending DMA writes to complete, and thus provides a mechanism to
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strictly order DMA from a device across all intervening busses and
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bridges. This barrier is not specific to a particular type of
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interconnect, it applies to the system as a whole, and so its
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-implementation must account for the idiosyncracies of the system all
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+implementation must account for the idiosyncrasies of the system all
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the way from the DMA device to memory.
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As an example of a situation where DMA_ATTR_WRITE_BARRIER would be
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@@ -60,7 +60,7 @@ such mapping is non-trivial task and consumes very limited resources
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Buffers allocated with this attribute can be only passed to user space
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by calling dma_mmap_attrs(). By using this API, you are guaranteeing
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that you won't dereference the pointer returned by dma_alloc_attr(). You
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-can threat it as a cookie that must be passed to dma_mmap_attrs() and
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+can treat it as a cookie that must be passed to dma_mmap_attrs() and
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dma_free_attrs(). Make sure that both of these also get this attribute
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set on each call.
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@@ -82,7 +82,7 @@ to 'device' domain, what synchronizes CPU caches for the given region
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(usually it means that the cache has been flushed or invalidated
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depending on the dma direction). However, next calls to
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dma_map_{single,page,sg}() for other devices will perform exactly the
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-same sychronization operation on the CPU cache. CPU cache sychronization
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+same synchronization operation on the CPU cache. CPU cache synchronization
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might be a time consuming operation, especially if the buffers are
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large, so it is highly recommended to avoid it if possible.
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DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of
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