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@@ -43,7 +43,7 @@ static struct platform_device pcit_serial8250_device = {
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};
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static struct plat_serial8250_port pcit_cplus_data[] = {
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- PORT(0x3f8, 4),
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+ PORT(0x3f8, 0),
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PORT(0x2f8, 3),
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PORT(0x3e8, 4),
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PORT(0x2e8, 3),
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@@ -59,9 +59,9 @@ static struct platform_device pcit_cplus_serial8250_device = {
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};
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static struct resource sni_io_resource = {
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- .start = 0x00001000UL,
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+ .start = 0x00000000UL,
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.end = 0x03bfffffUL,
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- .name = "PCIT IO MEM",
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+ .name = "PCIT IO",
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.flags = IORESOURCE_IO,
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};
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@@ -91,6 +91,11 @@ static struct resource pcit_io_resources[] = {
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.end = 0xdf,
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.name = "dma2",
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.flags = IORESOURCE_BUSY
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+ }, {
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+ .start = 0xcf8,
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+ .end = 0xcfb,
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+ .name = "PCI config addr",
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+ .flags = IORESOURCE_BUSY
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}, {
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.start = 0xcfc,
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.end = 0xcff,
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@@ -100,107 +105,19 @@ static struct resource pcit_io_resources[] = {
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};
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static struct resource sni_mem_resource = {
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- .start = 0x10000000UL,
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- .end = 0xffffffffUL,
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+ .start = 0x18000000UL,
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+ .end = 0x1fbfffffUL,
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.name = "PCIT PCI MEM",
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.flags = IORESOURCE_MEM
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};
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-/*
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- * The RM200/RM300 has a few holes in it's PCI/EISA memory address space used
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- * for other purposes. Be paranoid and allocate all of the before the PCI
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- * code gets a chance to to map anything else there ...
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- *
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- * This leaves the following areas available:
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- *
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- * 0x10000000 - 0x1009ffff (640kB) PCI/EISA/ISA Bus Memory
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- * 0x10100000 - 0x13ffffff ( 15MB) PCI/EISA/ISA Bus Memory
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- * 0x18000000 - 0x1fbfffff (124MB) PCI/EISA Bus Memory
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- * 0x1ff08000 - 0x1ffeffff (816kB) PCI/EISA Bus Memory
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- * 0xa0000000 - 0xffffffff (1.5GB) PCI/EISA Bus Memory
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- */
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-static struct resource pcit_mem_resources[] = {
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- {
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- .start = 0x14000000,
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- .end = 0x17bfffff,
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- .name = "PCI IO",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x17c00000,
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- .end = 0x17ffffff,
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- .name = "Cache Replacement Area",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x180a0000,
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- .end = 0x180bffff,
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- .name = "Video RAM area",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x180c0000,
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- .end = 0x180fffff,
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- .name = "ISA Reserved",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x19000000,
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- .end = 0x1fbfffff,
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- .name = "PCI MEM",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1fc00000,
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- .end = 0x1fc7ffff,
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- .name = "Boot PROM",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1fc80000,
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- .end = 0x1fcfffff,
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- .name = "Diag PROM",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1fd00000,
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- .end = 0x1fdfffff,
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- .name = "X-Bus",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1fe00000,
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- .end = 0x1fefffff,
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- .name = "BIOS map",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1ff00000,
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- .end = 0x1ff7ffff,
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- .name = "NVRAM / EEPROM",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1fff0000,
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- .end = 0x1fffefff,
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- .name = "MAUI ASIC",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x1ffff000,
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- .end = 0x1fffffff,
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- .name = "MP Agent",
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- .flags = IORESOURCE_BUSY
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- }, {
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- .start = 0x20000000,
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- .end = 0x9fffffff,
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- .name = "Main Memory",
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- .flags = IORESOURCE_BUSY
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- }
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-};
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-
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static void __init sni_pcit_resource_init(void)
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{
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int i;
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/* request I/O space for devices used on all i[345]86 PCs */
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for (i = 0; i < ARRAY_SIZE(pcit_io_resources); i++)
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- request_resource(&ioport_resource, pcit_io_resources + i);
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-
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- /* request mem space for pcimt-specific devices */
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- for (i = 0; i < ARRAY_SIZE(pcit_mem_resources); i++)
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- request_resource(&sni_mem_resource, pcit_mem_resources + i);
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-
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- ioport_resource.end = sni_io_resource.end;
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+ request_resource(&sni_io_resource, pcit_io_resources + i);
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}
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@@ -209,9 +126,10 @@ extern struct pci_ops sni_pcit_ops;
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static struct pci_controller sni_pcit_controller = {
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.pci_ops = &sni_pcit_ops,
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.mem_resource = &sni_mem_resource,
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- .mem_offset = 0x10000000UL,
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+ .mem_offset = 0x00000000UL,
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.io_resource = &sni_io_resource,
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- .io_offset = 0x00000000UL
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+ .io_offset = 0x00000000UL,
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+ .io_map_base = SNI_PORT_BASE
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};
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static void enable_pcit_irq(unsigned int irq)
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@@ -262,7 +180,7 @@ static void pcit_hwint0(void)
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int irq;
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clear_c0_status(IE_IRQ0);
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- irq = ffs((pending >> 16) & 0x7f);
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+ irq = ffs((pending >> 16) & 0x3f);
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if (likely(irq > 0))
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do_IRQ (irq + SNI_PCIT_INT_START - 1);
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@@ -289,6 +207,8 @@ static void sni_pcit_hwint_cplus(void)
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if (pending & C_IRQ0)
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pcit_hwint0();
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+ else if (pending & C_IRQ1)
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+ do_IRQ (MIPS_CPU_IRQ_BASE + 3);
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else if (pending & C_IRQ2)
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do_IRQ (MIPS_CPU_IRQ_BASE + 4);
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else if (pending & C_IRQ3)
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@@ -317,21 +237,23 @@ void __init sni_pcit_cplus_irq_init(void)
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mips_cpu_irq_init();
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for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
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set_irq_chip(i, &pcit_irq_type);
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- *(volatile u32 *)SNI_PCIT_INT_REG = 0;
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+ *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
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sni_hwint = sni_pcit_hwint_cplus;
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change_c0_status(ST0_IM, IE_IRQ0);
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- setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq);
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+ setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
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}
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void sni_pcit_init(void)
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{
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- sni_pcit_resource_init();
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rtc_mips_get_time = mc146818_get_cmos_time;
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rtc_mips_set_time = mc146818_set_rtc_mmss;
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board_time_init = sni_cpu_time_init;
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+ ioport_resource.end = sni_io_resource.end;
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#ifdef CONFIG_PCI
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+ PCIBIOS_MIN_IO = 0x9000;
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register_pci_controller(&sni_pcit_controller);
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#endif
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+ sni_pcit_resource_init();
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}
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static int __init snirm_pcit_setup_devinit(void)
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