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@@ -232,105 +232,10 @@ static unsigned long schizo_iclr_offset(unsigned long ino)
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return SCHIZO_ICLR_BASE + (ino * 8UL);
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}
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-/* PCI SCHIZO INO number to Sparc PIL level. This table only matters for
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- * INOs which will not have an associated PCI device struct, ie. onboard
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- * EBUS devices and PCI controller internal error interrupts.
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- */
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-static unsigned char schizo_pil_table[] = {
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-/*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */
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-/*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */
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-/*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */
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-/*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */
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-/*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */
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-/*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */
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-/*0x18*/5, /* SCSI */
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-/*0x19*/5, /* second SCSI */
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-/*0x1a*/0, /* UNKNOWN */
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-/*0x1b*/0, /* UNKNOWN */
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-/*0x1c*/8, /* Parallel */
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-/*0x1d*/5, /* Ethernet */
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-/*0x1e*/8, /* Firewire-1394 */
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-/*0x1f*/9, /* USB */
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-/*0x20*/13, /* Audio Record */
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-/*0x21*/14, /* Audio Playback */
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-/*0x22*/12, /* Serial */
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-/*0x23*/5, /* EBUS I2C */
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-/*0x24*/10, /* RTC Clock */
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-/*0x25*/11, /* Floppy */
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-/*0x26*/0, /* UNKNOWN */
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-/*0x27*/0, /* UNKNOWN */
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-/*0x28*/0, /* UNKNOWN */
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-/*0x29*/0, /* UNKNOWN */
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-/*0x2a*/10, /* UPA 1 */
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-/*0x2b*/10, /* UPA 2 */
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-/*0x2c*/0, /* UNKNOWN */
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-/*0x2d*/0, /* UNKNOWN */
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-/*0x2e*/0, /* UNKNOWN */
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-/*0x2f*/0, /* UNKNOWN */
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-/*0x30*/15, /* Uncorrectable ECC */
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-/*0x31*/15, /* Correctable ECC */
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-/*0x32*/15, /* PCI Bus A Error */
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-/*0x33*/15, /* PCI Bus B Error */
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-/*0x34*/15, /* Safari Bus Error */
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-/*0x35*/0, /* Reserved */
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-/*0x36*/0, /* Reserved */
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-/*0x37*/0, /* Reserved */
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-/*0x38*/0, /* Reserved for NewLink */
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-/*0x39*/0, /* Reserved for NewLink */
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-/*0x3a*/0, /* Reserved for NewLink */
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-/*0x3b*/0, /* Reserved for NewLink */
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-/*0x3c*/0, /* Reserved for NewLink */
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-/*0x3d*/0, /* Reserved for NewLink */
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-/*0x3e*/0, /* Reserved for NewLink */
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-/*0x3f*/0, /* Reserved for NewLink */
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-};
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-
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-static int schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
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-{
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- int ret;
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-
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- if (pdev &&
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- pdev->vendor == PCI_VENDOR_ID_SUN &&
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- pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
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- return 9;
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-
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- ret = schizo_pil_table[ino];
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- if (ret == 0 && pdev == NULL) {
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- ret = 5;
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- } else if (ret == 0) {
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- switch ((pdev->class >> 16) & 0xff) {
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- case PCI_BASE_CLASS_STORAGE:
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- ret = 5;
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- break;
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-
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- case PCI_BASE_CLASS_NETWORK:
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- ret = 6;
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- break;
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-
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- case PCI_BASE_CLASS_DISPLAY:
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- ret = 9;
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- break;
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-
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- case PCI_BASE_CLASS_MULTIMEDIA:
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- case PCI_BASE_CLASS_MEMORY:
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- case PCI_BASE_CLASS_BRIDGE:
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- case PCI_BASE_CLASS_SERIAL:
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- ret = 10;
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- break;
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-
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- default:
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- ret = 5;
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- break;
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- };
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- }
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-
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- return ret;
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-}
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-
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-static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2)
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+static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
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{
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unsigned long sync_reg = (unsigned long) _arg2;
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- u64 mask = 1UL << (__irq_ino(__irq(bucket)) & IMAP_INO);
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+ u64 mask = 1UL << (ino & IMAP_INO);
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u64 val;
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int limit;
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@@ -365,30 +270,33 @@ static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void
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}
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}
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+static unsigned long schizo_ino_to_iclr(struct pci_pbm_info *pbm,
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+ unsigned int ino)
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+{
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+ ino &= PCI_IRQ_INO;
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+ return pbm->pbm_regs + schizo_iclr_offset(ino) + 4;
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+}
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+
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+static unsigned long schizo_ino_to_imap(struct pci_pbm_info *pbm,
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+ unsigned int ino)
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+{
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+ ino &= PCI_IRQ_INO;
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+ return pbm->pbm_regs + schizo_imap_offset(ino) + 4;
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+}
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+
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static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
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struct pci_dev *pdev,
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unsigned int ino)
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{
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- struct ino_bucket *bucket;
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unsigned long imap, iclr;
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- unsigned long imap_off, iclr_off;
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- int pil, ign_fixup;
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+ int ign_fixup;
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+ int virt_irq;
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ino &= PCI_IRQ_INO;
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- imap_off = schizo_imap_offset(ino);
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/* Now build the IRQ bucket. */
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- pil = schizo_ino_to_pil(pdev, ino);
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-
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- if (PIL_RESERVED(pil))
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- BUG();
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-
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- imap = pbm->pbm_regs + imap_off;
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- imap += 4;
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-
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- iclr_off = schizo_iclr_offset(ino);
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- iclr = pbm->pbm_regs + iclr_off;
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- iclr += 4;
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+ imap = schizo_ino_to_imap(pbm, ino);
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+ iclr = schizo_ino_to_iclr(pbm, ino);
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/* On Schizo, no inofixup occurs. This is because each
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* INO has it's own IMAP register. On Psycho and Sabre
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@@ -405,19 +313,17 @@ static unsigned int schizo_irq_build(struct pci_pbm_info *pbm,
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ign_fixup = (1 << 6);
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}
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- bucket = __bucket(build_irq(pil, ign_fixup, iclr, imap));
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- bucket->flags |= IBF_PCI;
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+ virt_irq = build_irq(ign_fixup, iclr, imap);
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if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
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- struct irq_desc *p = bucket->irq_info;
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-
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- p->pre_handler = tomatillo_wsync_handler;
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- p->pre_handler_arg1 = ((pbm->chip_version <= 4) ?
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- (void *) 1 : (void *) 0);
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- p->pre_handler_arg2 = (void *) pbm->sync_reg;
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+ irq_install_pre_handler(virt_irq,
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+ tomatillo_wsync_handler,
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+ ((pbm->chip_version <= 4) ?
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+ (void *) 1 : (void *) 0),
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+ (void *) pbm->sync_reg);
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}
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- return __irq(bucket);
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+ return virt_irq;
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}
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/* SCHIZO error handling support. */
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@@ -458,7 +364,6 @@ struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
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static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
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{
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struct pci_pbm_info *pbm;
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- struct ino_bucket *bucket;
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unsigned long iclr;
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/* Do not clear the interrupt for the other PCI bus.
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@@ -476,11 +381,11 @@ static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq)
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else
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pbm = &p->pbm_A;
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- irq = schizo_irq_build(pbm, NULL,
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- (pbm->portid << 6) | (irq & IMAP_INO));
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- bucket = __bucket(irq);
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- iclr = bucket->iclr;
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+ schizo_irq_build(pbm, NULL,
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+ (pbm->portid << 6) | (irq & IMAP_INO));
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+ iclr = schizo_ino_to_iclr(pbm,
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+ (pbm->portid << 6) | (irq & IMAP_INO));
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upa_writel(ICLR_IDLE, iclr);
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}
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@@ -1225,7 +1130,6 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
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{
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struct pci_pbm_info *pbm;
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unsigned int irq;
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- struct ino_bucket *bucket;
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u64 tmp, err_mask, err_no_mask;
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/* Build IRQs and register handlers. */
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@@ -1237,8 +1141,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
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upa_writel(tmp, (pbm->pbm_regs +
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schizo_imap_offset(SCHIZO_UE_INO) + 4));
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@@ -1250,8 +1153,7 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
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upa_writel(tmp, (pbm->pbm_regs +
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schizo_imap_offset(SCHIZO_CE_INO) + 4));
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@@ -1264,8 +1166,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
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+ SCHIZO_PCIERR_A_INO)));
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upa_writel(tmp, (pbm->pbm_regs +
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schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
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@@ -1278,8 +1180,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
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+ SCHIZO_PCIERR_B_INO)));
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upa_writel(tmp, (pbm->pbm_regs +
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schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
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@@ -1291,8 +1193,8 @@ static void tomatillo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, ((pbm->portid << 6) |
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+ SCHIZO_SERR_INO)));
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upa_writel(tmp, (pbm->pbm_regs +
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schizo_imap_offset(SCHIZO_SERR_INO) + 4));
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@@ -1363,7 +1265,6 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
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{
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struct pci_pbm_info *pbm;
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unsigned int irq;
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- struct ino_bucket *bucket;
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u64 tmp, err_mask, err_no_mask;
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/* Build IRQs and register handlers. */
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@@ -1375,8 +1276,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_UE_INO));
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upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
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pbm = pbm_for_ino(p, SCHIZO_CE_INO);
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@@ -1387,8 +1287,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_CE_INO));
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upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
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pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
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@@ -1399,8 +1298,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO));
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upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
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pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
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@@ -1411,8 +1309,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO));
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upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
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pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
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@@ -1423,8 +1320,7 @@ static void schizo_register_error_handlers(struct pci_controller_info *p)
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pbm->name);
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prom_halt();
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}
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- bucket = __bucket(irq);
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- tmp = upa_readl(bucket->imap);
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+ tmp = upa_readl(schizo_ino_to_imap(pbm, (pbm->portid << 6) | SCHIZO_SERR_INO));
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upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
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/* Enable UE and CE interrupts for controller. */
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