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@@ -56,8 +56,8 @@
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#include "bnx2_fw.h"
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#define DRV_MODULE_NAME "bnx2"
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-#define DRV_MODULE_VERSION "2.0.18"
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-#define DRV_MODULE_RELDATE "Oct 7, 2010"
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+#define DRV_MODULE_VERSION "2.0.20"
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+#define DRV_MODULE_RELDATE "Nov 24, 2010"
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#define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-6.0.15.fw"
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#define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-6.0.15.fw"
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#define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-6.0.17.fw"
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@@ -4683,7 +4683,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
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val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
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BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
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- pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
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+ REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
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} else {
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val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
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@@ -7924,15 +7924,15 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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goto err_out_release;
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}
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+ bnx2_set_power_state(bp, PCI_D0);
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+
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/* Configure byte swap and enable write to the reg_window registers.
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* Rely on CPU to do target byte swapping on big endian systems
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* The chip's target access swapping will not swap all accesses
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*/
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- pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
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- BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
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- BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
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-
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- bnx2_set_power_state(bp, PCI_D0);
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+ REG_WR(bp, BNX2_PCICFG_MISC_CONFIG,
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+ BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
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+ BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
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bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
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