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@@ -27,7 +27,7 @@
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* m4 nvc0_grhub.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grhub.fuc.h
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*/
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-.section nvc0_grhub_data
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+.section #nvc0_grhub_data
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include(`nvc0_graph.fuc')
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gpc_count: .b32 0
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rop_count: .b32 0
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@@ -39,26 +39,26 @@ ctx_current: .b32 0
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chipsets:
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.b8 0xc0 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc0_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc0_hub_mmio_tail
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.b8 0xc1 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc1_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc1_hub_mmio_tail
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.b8 0xc3 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc0_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc0_hub_mmio_tail
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.b8 0xc4 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc0_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc0_hub_mmio_tail
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.b8 0xc8 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc0_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc0_hub_mmio_tail
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.b8 0xce 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc0_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc0_hub_mmio_tail
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.b8 0xcf 0 0 0
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-.b16 nvc0_hub_mmio_head
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-.b16 nvc0_hub_mmio_tail
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+.b16 #nvc0_hub_mmio_head
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+.b16 #nvc0_hub_mmio_tail
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.b8 0 0 0 0
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nvc0_hub_mmio_head:
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@@ -113,8 +113,8 @@ chan_mmio_address: .b32 0
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.align 256
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xfer_data: .b32 0
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-.section nvc0_grhub_code
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-bra init
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+.section #nvc0_grhub_code
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+bra #init
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define(`include_code')
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include(`nvc0_graph.fuc')
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@@ -157,7 +157,7 @@ init:
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iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE
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// setup i0 handler, and route all interrupts to it
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- mov $r1 ih
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+ mov $r1 #ih
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mov $iv0 $r1
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mov $r1 0x400
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iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH
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@@ -201,11 +201,11 @@ init:
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// fetch enabled GPC/ROP counts
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mov $r14 -0x69fc // 0x409604
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sethi $r14 0x400000
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- call nv_rd32
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+ call #nv_rd32
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extr $r1 $r15 16:20
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- st b32 D[$r0 + rop_count] $r1
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+ st b32 D[$r0 + #rop_count] $r1
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and $r15 0x1f
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- st b32 D[$r0 + gpc_count] $r15
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+ st b32 D[$r0 + #gpc_count] $r15
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// set BAR_REQMASK to GPC mask
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mov $r1 1
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@@ -220,14 +220,14 @@ init:
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mov $r2 0x800
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shl b32 $r2 6
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iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0]
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- mov $r15 chipsets - 8
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+ mov $r15 #chipsets - 8
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init_find_chipset:
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add b32 $r15 8
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ld b32 $r3 D[$r15 + 0x00]
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cmpu b32 $r3 $r2
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- bra e init_context
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+ bra e #init_context
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cmpu b32 $r3 0
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- bra ne init_find_chipset
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+ bra ne #init_find_chipset
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// unknown chipset
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ret
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@@ -239,9 +239,9 @@ init:
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ld b16 $r14 D[$r15 + 4]
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ld b16 $r15 D[$r15 + 6]
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sethi $r14 0
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- st b32 D[$r0 + hub_mmio_list_head] $r14
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- st b32 D[$r0 + hub_mmio_list_tail] $r15
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- call mmctx_size
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+ st b32 D[$r0 + #hub_mmio_list_head] $r14
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+ st b32 D[$r0 + #hub_mmio_list_tail] $r15
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+ call #mmctx_size
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// set mmctx base addresses now so we don't have to do it later,
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// they don't (currently) ever change
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@@ -260,7 +260,7 @@ init:
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add b32 $r1 1
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shl b32 $r1 8
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mov b32 $r15 $r1
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- call strand_ctx_init
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+ call #strand_ctx_init
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add b32 $r1 $r15
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// initialise each GPC in sequence by passing in the offset of its
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@@ -271,40 +271,40 @@ init:
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// when it has completed, and return the size of its context data
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// in GPCn_CC_SCRATCH[1]
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//
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- ld b32 $r3 D[$r0 + gpc_count]
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+ ld b32 $r3 D[$r0 + #gpc_count]
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mov $r4 0x2000
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sethi $r4 0x500000
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init_gpc:
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// setup, and start GPC ucode running
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add b32 $r14 $r4 0x804
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mov b32 $r15 $r1
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- call nv_wr32 // CC_SCRATCH[1] = ctx offset
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+ call #nv_wr32 // CC_SCRATCH[1] = ctx offset
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add b32 $r14 $r4 0x800
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mov b32 $r15 $r2
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- call nv_wr32 // CC_SCRATCH[0] = chipset
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+ call #nv_wr32 // CC_SCRATCH[0] = chipset
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add b32 $r14 $r4 0x10c
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clear b32 $r15
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- call nv_wr32
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+ call #nv_wr32
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add b32 $r14 $r4 0x104
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- call nv_wr32 // ENTRY
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+ call #nv_wr32 // ENTRY
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add b32 $r14 $r4 0x100
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mov $r15 2 // CTRL_START_TRIGGER
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- call nv_wr32 // CTRL
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+ call #nv_wr32 // CTRL
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// wait for it to complete, and adjust context size
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add b32 $r14 $r4 0x800
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init_gpc_wait:
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- call nv_rd32
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+ call #nv_rd32
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xbit $r15 $r15 31
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- bra e init_gpc_wait
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+ bra e #init_gpc_wait
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add b32 $r14 $r4 0x804
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- call nv_rd32
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+ call #nv_rd32
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add b32 $r1 $r15
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// next!
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add b32 $r4 0x8000
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sub b32 $r3 1
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- bra ne init_gpc
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+ bra ne #init_gpc
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// save context size, and tell host we're ready
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mov $r2 0x800
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@@ -322,13 +322,13 @@ main:
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// sleep until we have something to do
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bset $flags $p0
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sleep $p0
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- mov $r13 cmd_queue
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- call queue_get
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- bra $p1 main
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+ mov $r13 #cmd_queue
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+ call #queue_get
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+ bra $p1 #main
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// context switch, requested by GPU?
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cmpu b32 $r14 0x4001
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- bra ne main_not_ctx_switch
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+ bra ne #main_not_ctx_switch
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trace_set(T_AUTO)
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mov $r1 0xb00
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shl b32 $r1 6
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@@ -336,39 +336,39 @@ main:
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iord $r1 I[$r1 + 0x000] // CHAN_CUR
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xbit $r3 $r1 31
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- bra e chsw_no_prev
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+ bra e #chsw_no_prev
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xbit $r3 $r2 31
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- bra e chsw_prev_no_next
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+ bra e #chsw_prev_no_next
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push $r2
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mov b32 $r2 $r1
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trace_set(T_SAVE)
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bclr $flags $p1
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bset $flags $p2
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- call ctx_xfer
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+ call #ctx_xfer
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trace_clr(T_SAVE);
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pop $r2
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trace_set(T_LOAD);
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bset $flags $p1
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- call ctx_xfer
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+ call #ctx_xfer
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trace_clr(T_LOAD);
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- bra chsw_done
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+ bra #chsw_done
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chsw_prev_no_next:
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push $r2
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mov b32 $r2 $r1
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bclr $flags $p1
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bclr $flags $p2
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- call ctx_xfer
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+ call #ctx_xfer
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pop $r2
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mov $r1 0xb00
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shl b32 $r1 6
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iowr I[$r1] $r2
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- bra chsw_done
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+ bra #chsw_done
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chsw_no_prev:
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xbit $r3 $r2 31
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- bra e chsw_done
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+ bra e #chsw_done
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bset $flags $p1
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bclr $flags $p2
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- call ctx_xfer
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+ call #ctx_xfer
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// ack the context switch request
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chsw_done:
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@@ -377,32 +377,32 @@ main:
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mov $r2 1
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iowr I[$r1 + 0x000] $r2 // 0x409b0c
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trace_clr(T_AUTO)
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- bra main
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+ bra #main
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// request to set current channel? (*not* a context switch)
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main_not_ctx_switch:
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cmpu b32 $r14 0x0001
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- bra ne main_not_ctx_chan
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+ bra ne #main_not_ctx_chan
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mov b32 $r2 $r15
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- call ctx_chan
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- bra main_done
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+ call #ctx_chan
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+ bra #main_done
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// request to store current channel context?
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main_not_ctx_chan:
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cmpu b32 $r14 0x0002
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- bra ne main_not_ctx_save
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+ bra ne #main_not_ctx_save
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trace_set(T_SAVE)
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bclr $flags $p1
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bclr $flags $p2
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- call ctx_xfer
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+ call #ctx_xfer
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trace_clr(T_SAVE)
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- bra main_done
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+ bra #main_done
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main_not_ctx_save:
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shl b32 $r15 $r14 16
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or $r15 E_BAD_COMMAND
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- call error
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- bra main
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+ call #error
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+ bra #main
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main_done:
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mov $r1 0x820
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@@ -410,7 +410,7 @@ main:
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clear b32 $r2
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bset $r2 31
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iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000
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- bra main
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+ bra #main
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// interrupt handler
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ih:
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@@ -427,13 +427,13 @@ ih:
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// incoming fifo command?
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iord $r10 I[$r0 + 0x200] // INTR
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and $r11 $r10 0x00000004
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- bra e ih_no_fifo
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+ bra e #ih_no_fifo
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// queue incoming fifo command for later processing
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mov $r11 0x1900
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- mov $r13 cmd_queue
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+ mov $r13 #cmd_queue
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iord $r14 I[$r11 + 0x100] // FIFO_CMD
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iord $r15 I[$r11 + 0x000] // FIFO_DATA
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- call queue_put
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+ call #queue_put
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add b32 $r11 0x400
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mov $r14 1
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iowr I[$r11 + 0x000] $r14 // FIFO_ACK
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@@ -441,18 +441,18 @@ ih:
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// context switch request?
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ih_no_fifo:
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and $r11 $r10 0x00000100
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- bra e ih_no_ctxsw
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+ bra e #ih_no_ctxsw
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// enqueue a context switch for later processing
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- mov $r13 cmd_queue
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+ mov $r13 #cmd_queue
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mov $r14 0x4001
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- call queue_put
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+ call #queue_put
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// anything we didn't handle, bring it to the host's attention
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ih_no_ctxsw:
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mov $r11 0x104
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not b32 $r11
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and $r11 $r10 $r11
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- bra e ih_no_other
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+ bra e #ih_no_other
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mov $r10 0xc1c
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shl b32 $r10 6
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iowr I[$r10] $r11 // INTR_UP_SET
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@@ -478,11 +478,11 @@ ctx_4160s:
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mov $r14 0x4160
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sethi $r14 0x400000
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mov $r15 1
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- call nv_wr32
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+ call #nv_wr32
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ctx_4160s_wait:
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- call nv_rd32
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+ call #nv_rd32
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xbit $r15 $r15 4
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- bra e ctx_4160s_wait
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+ bra e #ctx_4160s_wait
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ret
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// Without clearing again at end of xfer, some things cause PGRAPH
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@@ -492,7 +492,7 @@ ctx_4160c:
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mov $r14 0x4160
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sethi $r14 0x400000
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clear b32 $r15
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- call nv_wr32
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+ call #nv_wr32
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ret
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// Again, not real sure
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@@ -503,7 +503,7 @@ ctx_4170s:
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mov $r14 0x4170
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sethi $r14 0x400000
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or $r15 0x10
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- call nv_wr32
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+ call #nv_wr32
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ret
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// Waits for a ctx_4170s() call to complete
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@@ -511,9 +511,9 @@ ctx_4170s:
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ctx_4170w:
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mov $r14 0x4170
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sethi $r14 0x400000
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- call nv_rd32
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+ call #nv_rd32
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and $r15 0x10
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- bra ne ctx_4170w
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+ bra ne #ctx_4170w
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ret
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// Disables various things, waits a bit, and re-enables them..
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@@ -530,7 +530,7 @@ ctx_redswitch:
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mov $r15 8
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ctx_redswitch_delay:
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sub b32 $r15 1
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- bra ne ctx_redswitch_delay
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+ bra ne #ctx_redswitch_delay
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mov $r15 0x770
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iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL
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ret
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@@ -546,10 +546,10 @@ ctx_86c:
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iowr I[$r14] $r15 // HUB(0x86c) = val
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mov $r14 -0x75ec
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sethi $r14 0x400000
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- call nv_wr32 // ROP(0xa14) = val
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+ call #nv_wr32 // ROP(0xa14) = val
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mov $r14 -0x5794
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sethi $r14 0x410000
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- call nv_wr32 // GPC(0x86c) = val
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+ call #nv_wr32 // GPC(0x86c) = val
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ret
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// ctx_load - load's a channel's ctxctl data, and selects its vm
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@@ -561,7 +561,7 @@ ctx_load:
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// switch to channel, somewhat magic in parts..
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mov $r10 12 // DONE_UNK12
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- call wait_donez
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+ call #wait_donez
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mov $r1 0xa24
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shl b32 $r1 6
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iowr I[$r1 + 0x000] $r0 // 0x409a24
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@@ -576,7 +576,7 @@ ctx_load:
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ctx_chan_wait_0:
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iord $r4 I[$r1 + 0x100]
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and $r4 0x1f
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- bra ne ctx_chan_wait_0
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+ bra ne #ctx_chan_wait_0
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iowr I[$r3 + 0x000] $r2 // CHAN_CUR
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// load channel header, fetch PGRAPH context pointer
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@@ -595,19 +595,19 @@ ctx_load:
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sethi $r2 0x80000000
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iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram
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mov $r1 0x10 // chan + 0x0210
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- mov $r2 xfer_data
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+ mov $r2 #xfer_data
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sethi $r2 0x00020000 // 16 bytes
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xdld $r1 $r2
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xdwait
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trace_clr(T_LCHAN)
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// update current context
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- ld b32 $r1 D[$r0 + xfer_data + 4]
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+ ld b32 $r1 D[$r0 + #xfer_data + 4]
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shl b32 $r1 24
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- ld b32 $r2 D[$r0 + xfer_data + 0]
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+ ld b32 $r2 D[$r0 + #xfer_data + 0]
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shr b32 $r2 8
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or $r1 $r2
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- st b32 D[$r0 + ctx_current] $r1
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+ st b32 D[$r0 + #ctx_current] $r1
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// set transfer base to start of context, and fetch context header
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trace_set(T_LCTXH)
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@@ -618,7 +618,7 @@ ctx_load:
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mov $r1 0xa20
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shl b32 $r1 6
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iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm
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- mov $r1 chan_data
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+ mov $r1 #chan_data
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sethi $r1 0x00060000 // 256 bytes
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xdld $r0 $r1
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xdwait
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@@ -635,10 +635,10 @@ ctx_load:
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// In: $r2 channel address
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//
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ctx_chan:
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- call ctx_4160s
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- call ctx_load
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+ call #ctx_4160s
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+ call #ctx_load
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mov $r10 12 // DONE_UNK12
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- call wait_donez
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+ call #wait_donez
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mov $r1 0xa10
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shl b32 $r1 6
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mov $r2 5
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@@ -646,8 +646,8 @@ ctx_chan:
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ctx_chan_wait:
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iord $r2 I[$r1 + 0x000]
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or $r2 $r2
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- bra ne ctx_chan_wait
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- call ctx_4160c
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+ bra ne #ctx_chan_wait
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+ call #ctx_4160c
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ret
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// Execute per-context state overrides list
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@@ -661,7 +661,7 @@ ctx_chan:
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//
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ctx_mmio_exec:
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// set transfer base to be the mmio list
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- ld b32 $r3 D[$r0 + chan_mmio_address]
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+ ld b32 $r3 D[$r0 + #chan_mmio_address]
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mov $r2 0xa04
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shl b32 $r2 6
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iowr I[$r2 + 0x000] $r3 // MEM_BASE
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@@ -670,31 +670,31 @@ ctx_mmio_exec:
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ctx_mmio_loop:
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// fetch next 256 bytes of mmio list if necessary
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and $r4 $r3 0xff
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- bra ne ctx_mmio_pull
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- mov $r5 xfer_data
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+ bra ne #ctx_mmio_pull
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+ mov $r5 #xfer_data
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sethi $r5 0x00060000 // 256 bytes
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xdld $r3 $r5
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xdwait
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// execute a single list entry
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ctx_mmio_pull:
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- ld b32 $r14 D[$r4 + xfer_data + 0x00]
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- ld b32 $r15 D[$r4 + xfer_data + 0x04]
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- call nv_wr32
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+ ld b32 $r14 D[$r4 + #xfer_data + 0x00]
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+ ld b32 $r15 D[$r4 + #xfer_data + 0x04]
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+ call #nv_wr32
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// next!
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add b32 $r3 8
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sub b32 $r1 1
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- bra ne ctx_mmio_loop
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+ bra ne #ctx_mmio_loop
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// set transfer base back to the current context
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ctx_mmio_done:
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- ld b32 $r3 D[$r0 + ctx_current]
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+ ld b32 $r3 D[$r0 + #ctx_current]
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iowr I[$r2 + 0x000] $r3 // MEM_BASE
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// disable the mmio list now, we don't need/want to execute it again
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- st b32 D[$r0 + chan_mmio_count] $r0
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- mov $r1 chan_data
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+ st b32 D[$r0 + #chan_mmio_count] $r0
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+ mov $r1 #chan_data
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sethi $r1 0x00060000 // 256 bytes
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xdst $r0 $r1
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xdwait
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@@ -709,46 +709,46 @@ ctx_mmio_exec:
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// on load it means: "a save preceeded this load"
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//
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ctx_xfer:
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- bra not $p1 ctx_xfer_pre
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- bra $p2 ctx_xfer_pre_load
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+ bra not $p1 #ctx_xfer_pre
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+ bra $p2 #ctx_xfer_pre_load
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ctx_xfer_pre:
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mov $r15 0x10
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- call ctx_86c
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- call ctx_4160s
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- bra not $p1 ctx_xfer_exec
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+ call #ctx_86c
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+ call #ctx_4160s
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+ bra not $p1 #ctx_xfer_exec
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ctx_xfer_pre_load:
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mov $r15 2
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- call ctx_4170s
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- call ctx_4170w
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- call ctx_redswitch
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+ call #ctx_4170s
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+ call #ctx_4170w
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+ call #ctx_redswitch
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clear b32 $r15
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- call ctx_4170s
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- call ctx_load
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+ call #ctx_4170s
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+ call #ctx_load
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// fetch context pointer, and initiate xfer on all GPCs
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ctx_xfer_exec:
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- ld b32 $r1 D[$r0 + ctx_current]
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+ ld b32 $r1 D[$r0 + #ctx_current]
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mov $r2 0x414
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shl b32 $r2 6
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iowr I[$r2 + 0x000] $r0 // BAR_STATUS = reset
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mov $r14 -0x5b00
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sethi $r14 0x410000
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mov b32 $r15 $r1
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- call nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer
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+ call #nv_wr32 // GPC_BCAST_WRCMD_DATA = ctx pointer
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add b32 $r14 4
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xbit $r15 $flags $p1
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xbit $r2 $flags $p2
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shl b32 $r2 1
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or $r15 $r2
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- call nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
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+ call #nv_wr32 // GPC_BCAST_WRCMD_CMD = GPC_XFER(type)
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// strands
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mov $r1 0x4afc
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sethi $r1 0x20000
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mov $r2 0xc
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iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c
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- call strand_wait
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+ call #strand_wait
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mov $r2 0x47fc
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sethi $r2 0x20000
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iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00
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@@ -760,22 +760,22 @@ ctx_xfer:
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xbit $r10 $flags $p1 // direction
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or $r10 6 // first, last
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mov $r11 0 // base = 0
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- ld b32 $r12 D[$r0 + hub_mmio_list_head]
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- ld b32 $r13 D[$r0 + hub_mmio_list_tail]
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+ ld b32 $r12 D[$r0 + #hub_mmio_list_head]
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+ ld b32 $r13 D[$r0 + #hub_mmio_list_tail]
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mov $r14 0 // not multi
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- call mmctx_xfer
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+ call #mmctx_xfer
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// wait for GPCs to all complete
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mov $r10 8 // DONE_BAR
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- call wait_doneo
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+ call #wait_doneo
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// wait for strand xfer to complete
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- call strand_wait
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+ call #strand_wait
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// post-op
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- bra $p1 ctx_xfer_post
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+ bra $p1 #ctx_xfer_post
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mov $r10 12 // DONE_UNK12
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- call wait_donez
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+ call #wait_donez
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mov $r1 0xa10
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shl b32 $r1 6
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mov $r2 5
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@@ -783,27 +783,27 @@ ctx_xfer:
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ctx_xfer_post_save_wait:
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iord $r2 I[$r1]
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or $r2 $r2
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- bra ne ctx_xfer_post_save_wait
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+ bra ne #ctx_xfer_post_save_wait
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- bra $p2 ctx_xfer_done
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+ bra $p2 #ctx_xfer_done
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ctx_xfer_post:
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mov $r15 2
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- call ctx_4170s
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+ call #ctx_4170s
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clear b32 $r15
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- call ctx_86c
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- call strand_post
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- call ctx_4170w
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+ call #ctx_86c
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+ call #strand_post
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+ call #ctx_4170w
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clear b32 $r15
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- call ctx_4170s
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+ call #ctx_4170s
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- bra not $p1 ctx_xfer_no_post_mmio
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- ld b32 $r1 D[$r0 + chan_mmio_count]
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+ bra not $p1 #ctx_xfer_no_post_mmio
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+ ld b32 $r1 D[$r0 + #chan_mmio_count]
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or $r1 $r1
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- bra e ctx_xfer_no_post_mmio
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- call ctx_mmio_exec
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+ bra e #ctx_xfer_no_post_mmio
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+ call #ctx_mmio_exec
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ctx_xfer_no_post_mmio:
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- call ctx_4160c
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+ call #ctx_4160c
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ctx_xfer_done:
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ret
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Ben Skeggs